nir: add a load_global_constant uniform intel variant

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23477>
This commit is contained in:
Lionel Landwerlin 2023-06-09 13:57:43 +03:00 committed by Marge Bot
parent 5ae8a78d8c
commit 4ee1a8bb9c
3 changed files with 7 additions and 0 deletions

View file

@ -214,6 +214,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr)
case nir_intrinsic_load_barycentric_optimize_amd:
case nir_intrinsic_load_poly_line_smooth_enabled:
case nir_intrinsic_load_rasterization_primitive_amd:
case nir_intrinsic_load_global_constant_uniform_block_intel:
is_divergent = false;
break;

View file

@ -1762,6 +1762,10 @@ store("ssbo_block_intel", [-1, 1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]
# src[] = { value, offset }.
store("shared_block_intel", [1], [BASE, WRITE_MASK, ALIGN_MUL, ALIGN_OFFSET])
# src[] = { address }.
load("global_constant_uniform_block_intel", [1],
[ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE, CAN_REORDER])
# Similar to load_global_const_block_intel but for UBOs
# offset should be uniform
# src[] = { buffer_index, offset }.

View file

@ -85,6 +85,7 @@ case nir_intrinsic_##op: {\
STORE(nir_var_mem_shared, shared, -1, 1, -1, 0)
LOAD(nir_var_mem_global, global, -1, 0, -1)
STORE(nir_var_mem_global, global, -1, 1, -1, 0)
LOAD(nir_var_mem_global, global_constant, -1, 0, -1)
LOAD(nir_var_mem_task_payload, task_payload, -1, 0, -1)
STORE(nir_var_mem_task_payload, task_payload, -1, 1, -1, 0)
ATOMIC(nir_var_mem_ssbo, ssbo, 0, 1, -1, 2)
@ -97,6 +98,7 @@ case nir_intrinsic_##op: {\
LOAD(nir_var_mem_ubo, ubo_uniform_block_intel, 0, 1, -1)
LOAD(nir_var_mem_ssbo, ssbo_uniform_block_intel, 0, 1, -1)
LOAD(nir_var_mem_shared, shared_uniform_block_intel, -1, 0, -1)
LOAD(nir_var_mem_global, global_constant_uniform_block_intel, -1, 0, -1)
default:
break;
#undef ATOMIC