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radeonsi: access descriptor sets via local variables
This will simplify moving them to a per-context array. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Nicolai Hähnle
parent
ba4a2840c7
commit
4e0fb72786
1 changed files with 41 additions and 31 deletions
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@ -336,13 +336,14 @@ static void si_set_sampler_view(struct si_context *sctx,
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{
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struct si_sampler_views *views = &sctx->samplers[shader].views;
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struct si_sampler_view *rview = (struct si_sampler_view*)view;
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struct si_descriptors *descs = &views->desc;
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if (views->views[slot] == view && !disallow_early_out)
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return;
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if (view) {
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struct r600_texture *rtex = (struct r600_texture *)view->texture;
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uint32_t *desc = views->desc.list + slot * 16;
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uint32_t *desc = descs->list + slot * 16;
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si_sampler_view_add_buffer(sctx, view->texture,
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RADEON_USAGE_READ);
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@ -380,13 +381,13 @@ static void si_set_sampler_view(struct si_context *sctx,
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views->enabled_mask |= 1u << slot;
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} else {
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pipe_sampler_view_reference(&views->views[slot], NULL);
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memcpy(views->desc.list + slot*16, null_texture_descriptor, 8*4);
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memcpy(descs->list + slot*16, null_texture_descriptor, 8*4);
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/* Only clear the lower dwords of FMASK. */
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memcpy(views->desc.list + slot*16 + 8, null_texture_descriptor, 4*4);
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memcpy(descs->list + slot*16 + 8, null_texture_descriptor, 4*4);
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views->enabled_mask &= ~(1u << slot);
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}
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views->desc.dirty_mask |= 1u << slot;
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descs->dirty_mask |= 1u << slot;
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}
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static bool is_compressed_colortex(struct r600_texture *rtex)
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@ -536,6 +537,7 @@ static void si_set_shader_image(struct si_context *ctx,
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{
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struct si_screen *screen = ctx->screen;
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struct si_images_info *images = &ctx->images[shader];
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struct si_descriptors *descs = &images->desc;
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struct r600_resource *res;
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if (!view || !view->resource) {
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@ -559,14 +561,14 @@ static void si_set_shader_image(struct si_context *ctx,
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view->format,
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view->u.buf.first_element,
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view->u.buf.last_element,
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images->desc.list + slot * 8);
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descs->list + slot * 8);
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images->compressed_colortex_mask &= ~(1 << slot);
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} else {
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static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
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struct r600_texture *tex = (struct r600_texture *)res;
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unsigned level;
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unsigned width, height, depth;
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uint32_t *desc = images->desc.list + slot * 8;
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uint32_t *desc = descs->list + slot * 8;
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assert(!tex->is_depth);
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assert(tex->fmask.size == 0);
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@ -616,7 +618,7 @@ static void si_set_shader_image(struct si_context *ctx,
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}
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images->enabled_mask |= 1u << slot;
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images->desc.dirty_mask |= 1u << slot;
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descs->dirty_mask |= 1u << slot;
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}
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static void
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@ -876,7 +878,8 @@ static void si_set_constant_buffer(struct si_context *sctx,
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struct si_buffer_resources *buffers,
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uint slot, struct pipe_constant_buffer *input)
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{
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assert(slot < buffers->desc.num_elements);
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struct si_descriptors *descs = &buffers->desc;
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assert(slot < descs->num_elements);
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pipe_resource_reference(&buffers->buffers[slot], NULL);
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/* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
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@ -908,7 +911,7 @@ static void si_set_constant_buffer(struct si_context *sctx,
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}
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/* Set the descriptor. */
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uint32_t *desc = buffers->desc.list + slot*4;
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uint32_t *desc = descs->list + slot*4;
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desc[0] = va;
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desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
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S_008F04_STRIDE(0);
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@ -927,11 +930,11 @@ static void si_set_constant_buffer(struct si_context *sctx,
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buffers->enabled_mask |= 1u << slot;
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} else {
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/* Clear the descriptor. */
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memset(buffers->desc.list + slot*4, 0, sizeof(uint32_t) * 4);
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memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
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buffers->enabled_mask &= ~(1u << slot);
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}
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buffers->desc.dirty_mask |= 1u << slot;
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descs->dirty_mask |= 1u << slot;
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}
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void si_set_rw_buffer(struct si_context *sctx,
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@ -960,6 +963,7 @@ static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
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struct si_descriptors *descs = &buffers->desc;
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unsigned i;
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assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
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@ -968,14 +972,14 @@ static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
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struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
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struct r600_resource *buf;
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unsigned slot = start_slot + i;
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uint32_t *desc = buffers->desc.list + slot * 4;
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uint32_t *desc = descs->list + slot * 4;
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uint64_t va;
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if (!sbuffer || !sbuffer->buffer) {
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pipe_resource_reference(&buffers->buffers[slot], NULL);
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memset(desc, 0, sizeof(uint32_t) * 4);
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buffers->enabled_mask &= ~(1u << slot);
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buffers->desc.dirty_mask |= 1u << slot;
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descs->dirty_mask |= 1u << slot;
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continue;
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}
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@ -997,7 +1001,7 @@ static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buf,
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buffers->shader_usage, buffers->priority);
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buffers->enabled_mask |= 1u << slot;
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buffers->desc.dirty_mask |= 1u << slot;
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descs->dirty_mask |= 1u << slot;
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}
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}
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@ -1011,11 +1015,12 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct si_buffer_resources *buffers = &sctx->rw_buffers;
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struct si_descriptors *descs = &buffers->desc;
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/* The stride field in the resource descriptor has 14 bits */
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assert(stride < (1 << 14));
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assert(slot < buffers->desc.num_elements);
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assert(slot < descs->num_elements);
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pipe_resource_reference(&buffers->buffers[slot], NULL);
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if (buffer) {
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@ -1063,7 +1068,7 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
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num_records *= stride;
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/* Set the descriptor. */
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uint32_t *desc = buffers->desc.list + slot*4;
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uint32_t *desc = descs->list + slot*4;
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desc[0] = va;
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desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
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S_008F04_STRIDE(stride) |
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@ -1086,11 +1091,11 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
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buffers->enabled_mask |= 1u << slot;
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} else {
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/* Clear the descriptor. */
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memset(buffers->desc.list + slot*4, 0, sizeof(uint32_t) * 4);
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memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
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buffers->enabled_mask &= ~(1u << slot);
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}
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buffers->desc.dirty_mask |= 1u << slot;
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descs->dirty_mask |= 1u << slot;
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}
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/* STREAMOUT BUFFERS */
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@ -1102,6 +1107,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct si_buffer_resources *buffers = &sctx->rw_buffers;
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struct si_descriptors *descs = &buffers->desc;
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unsigned old_num_targets = sctx->b.streamout.num_targets;
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unsigned i, bufidx;
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@ -1164,7 +1170,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
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* the buffer will be considered not bound and store
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* instructions will be no-ops.
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*/
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uint32_t *desc = buffers->desc.list + bufidx*4;
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uint32_t *desc = descs->list + bufidx*4;
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desc[0] = va;
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desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
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desc[2] = 0xffffffff;
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@ -1183,21 +1189,21 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
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buffers->enabled_mask |= 1u << bufidx;
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} else {
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/* Clear the descriptor and unset the resource. */
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memset(buffers->desc.list + bufidx*4, 0,
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memset(descs->list + bufidx*4, 0,
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sizeof(uint32_t) * 4);
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pipe_resource_reference(&buffers->buffers[bufidx],
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NULL);
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buffers->enabled_mask &= ~(1u << bufidx);
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}
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buffers->desc.dirty_mask |= 1u << bufidx;
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descs->dirty_mask |= 1u << bufidx;
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}
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for (; i < old_num_targets; i++) {
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bufidx = SI_VS_STREAMOUT_BUF0 + i;
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/* Clear the descriptor and unset the resource. */
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memset(buffers->desc.list + bufidx*4, 0, sizeof(uint32_t) * 4);
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memset(descs->list + bufidx*4, 0, sizeof(uint32_t) * 4);
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pipe_resource_reference(&buffers->buffers[bufidx], NULL);
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buffers->enabled_mask &= ~(1u << bufidx);
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buffers->desc.dirty_mask |= 1u << bufidx;
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descs->dirty_mask |= 1u << bufidx;
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}
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}
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@ -1261,15 +1267,16 @@ static void si_reset_buffer_resources(struct si_context *sctx,
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struct pipe_resource *buf,
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uint64_t old_va)
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{
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struct si_descriptors *descs = &buffers->desc;
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unsigned mask = buffers->enabled_mask;
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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if (buffers->buffers[i] == buf) {
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si_desc_reset_buffer_offset(&sctx->b.b,
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buffers->desc.list + i*4,
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descs->list + i*4,
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old_va, buf);
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buffers->desc.dirty_mask |= 1u << i;
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descs->dirty_mask |= 1u << i;
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource *)buf,
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@ -1324,13 +1331,14 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
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/* Streamout buffers. (other internal buffers can't be invalidated) */
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for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
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struct si_buffer_resources *buffers = &sctx->rw_buffers;
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struct si_descriptors *descs = &buffers->desc;
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if (buffers->buffers[i] != buf)
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continue;
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si_desc_reset_buffer_offset(ctx, buffers->desc.list + i*4,
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si_desc_reset_buffer_offset(ctx, descs->list + i*4,
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old_va, buf);
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buffers->desc.dirty_mask |= 1u << i;
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descs->dirty_mask |= 1u << i;
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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rbuffer, buffers->shader_usage,
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@ -1361,16 +1369,17 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
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/* Texture buffers - update bindings. */
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for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
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struct si_sampler_views *views = &sctx->samplers[shader].views;
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struct si_descriptors *descs = &views->desc;
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unsigned mask = views->enabled_mask;
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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if (views->views[i]->texture == buf) {
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si_desc_reset_buffer_offset(ctx,
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views->desc.list +
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descs->list +
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i * 16 + 4,
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old_va, buf);
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views->desc.dirty_mask |= 1u << i;
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descs->dirty_mask |= 1u << i;
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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rbuffer, RADEON_USAGE_READ,
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@ -1382,6 +1391,7 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
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/* Shader images */
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for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
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struct si_images_info *images = &sctx->images[shader];
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struct si_descriptors *descs = &images->desc;
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unsigned mask = images->enabled_mask;
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while (mask) {
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@ -1392,9 +1402,9 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
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si_mark_image_range_valid(&images->views[i]);
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si_desc_reset_buffer_offset(
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ctx, images->desc.list + i * 8 + 4,
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ctx, descs->list + i * 8 + 4,
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old_va, buf);
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images->desc.dirty_mask |= 1u << i;
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descs->dirty_mask |= 1u << i;
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radeon_add_to_buffer_list(
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&sctx->b, &sctx->b.gfx, rbuffer,
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