From 4d4b0dfdb8db790ba0c50d6d35fcadebc3ce7a2d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Thu, 27 Apr 2023 14:14:22 -0700 Subject: [PATCH] anv: Set memory types supported by Xe KMD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Due the lack of APIs to set mmap modes, Xe KMD can't support the same memory types as i915. So here adding a i915 and Xe function to set memory types supported by each KMD. Iris function iris_xe_bo_flags_to_mmap_mode() has a table with all the mmaps modes of each type of placement. Signed-off-by: José Roberto de Souza Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/vulkan/anv_device.c | 92 +++++------------------------- src/intel/vulkan/i915/anv_device.c | 79 +++++++++++++++++++++++++ src/intel/vulkan/i915/anv_device.h | 2 + src/intel/vulkan/xe/anv_device.c | 54 ++++++++++++++++++ src/intel/vulkan/xe/anv_device.h | 3 + 5 files changed, 151 insertions(+), 79 deletions(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index b5a77e2d751..61b2509df00 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -871,7 +871,6 @@ anv_update_meminfo(struct anv_physical_device *device, int fd) device->vram_non_mappable.available = devinfo->mem.vram.unmappable.free; } - static VkResult anv_physical_device_init_heaps(struct anv_physical_device *device, int fd) { @@ -913,65 +912,6 @@ anv_physical_device_init_heaps(struct anv_physical_device *device, int fd) .is_local_mem = true, }; } - - device->memory.type_count = 3; - device->memory.types[0] = (struct anv_memory_type) { - .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT, - .heapIndex = 0, - }; - device->memory.types[1] = (struct anv_memory_type) { - .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | - VK_MEMORY_PROPERTY_HOST_COHERENT_BIT | - VK_MEMORY_PROPERTY_HOST_CACHED_BIT, - .heapIndex = 1, - }; - device->memory.types[2] = (struct anv_memory_type) { - .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT | - VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | - VK_MEMORY_PROPERTY_HOST_COHERENT_BIT, - /* This memory type either comes from heaps[0] if there is only - * mappable vram region, or from heaps[2] if there is both mappable & - * non-mappable vram regions. - */ - .heapIndex = device->vram_non_mappable.size > 0 ? 2 : 0, - }; - } else if (device->info.has_llc) { - device->memory.heap_count = 1; - device->memory.heaps[0] = (struct anv_memory_heap) { - .size = device->sys.size, - .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT, - .is_local_mem = false, - }; - - /* Big core GPUs share LLC with the CPU and thus one memory type can be - * both cached and coherent at the same time. - * - * But some game engines can't handle single type well - * https://gitlab.freedesktop.org/mesa/mesa/-/issues/7360#note_1719438 - * - * The second memory type w/out HOST_CACHED_BIT will get write-combining. - * See anv_AllocateMemory()). - * - * The Intel Vulkan driver for Windows also advertises these memory types. - */ - device->memory.type_count = 3; - device->memory.types[0] = (struct anv_memory_type) { - .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT, - .heapIndex = 0, - }; - device->memory.types[1] = (struct anv_memory_type) { - .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT | - VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | - VK_MEMORY_PROPERTY_HOST_COHERENT_BIT, - .heapIndex = 0, - }; - device->memory.types[2] = (struct anv_memory_type) { - .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT | - VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | - VK_MEMORY_PROPERTY_HOST_COHERENT_BIT | - VK_MEMORY_PROPERTY_HOST_CACHED_BIT, - .heapIndex = 0, - }; } else { device->memory.heap_count = 1; device->memory.heaps[0] = (struct anv_memory_heap) { @@ -979,27 +919,21 @@ anv_physical_device_init_heaps(struct anv_physical_device *device, int fd) .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT, .is_local_mem = false, }; - - /* The spec requires that we expose a host-visible, coherent memory - * type, but Atom GPUs don't share LLC. Thus we offer two memory types - * to give the application a choice between cached, but not coherent and - * coherent but uncached (WC though). - */ - device->memory.type_count = 2; - device->memory.types[0] = (struct anv_memory_type) { - .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT | - VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | - VK_MEMORY_PROPERTY_HOST_CACHED_BIT, - .heapIndex = 0, - }; - device->memory.types[1] = (struct anv_memory_type) { - .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT | - VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | - VK_MEMORY_PROPERTY_HOST_COHERENT_BIT, - .heapIndex = 0, - }; } + switch (device->info.kmd_type) { + case INTEL_KMD_TYPE_XE: + result = anv_xe_physical_device_init_memory_types(device); + break; + case INTEL_KMD_TYPE_I915: + default: + result = anv_i915_physical_device_init_memory_types(device); + break; + } + + if (result != VK_SUCCESS) + return result; + for (unsigned i = 0; i < device->memory.type_count; i++) { VkMemoryPropertyFlags props = device->memory.types[i].propertyFlags; if ((props & VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT) && diff --git a/src/intel/vulkan/i915/anv_device.c b/src/intel/vulkan/i915/anv_device.c index 257b933d579..fbaec65b24a 100644 --- a/src/intel/vulkan/i915/anv_device.c +++ b/src/intel/vulkan/i915/anv_device.c @@ -125,6 +125,85 @@ anv_i915_physical_device_get_parameters(struct anv_physical_device *device) return result; } +VkResult +anv_i915_physical_device_init_memory_types(struct anv_physical_device *device) +{ + if (anv_physical_device_has_vram(device)) { + device->memory.type_count = 3; + device->memory.types[0] = (struct anv_memory_type) { + .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT, + .heapIndex = 0, + }; + device->memory.types[1] = (struct anv_memory_type) { + .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | + VK_MEMORY_PROPERTY_HOST_COHERENT_BIT | + VK_MEMORY_PROPERTY_HOST_CACHED_BIT, + .heapIndex = 1, + }; + device->memory.types[2] = (struct anv_memory_type) { + .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT | + VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | + VK_MEMORY_PROPERTY_HOST_COHERENT_BIT, + /* This memory type either comes from heaps[0] if there is only + * mappable vram region, or from heaps[2] if there is both mappable & + * non-mappable vram regions. + */ + .heapIndex = device->vram_non_mappable.size > 0 ? 2 : 0, + }; + } else if (device->info.has_llc) { + /* Big core GPUs share LLC with the CPU and thus one memory type can be + * both cached and coherent at the same time. + * + * But some game engines can't handle single type well + * https://gitlab.freedesktop.org/mesa/mesa/-/issues/7360#note_1719438 + * + * The second memory type w/out HOST_CACHED_BIT will get write-combining. + * See anv_AllocateMemory()). + * + * The Intel Vulkan driver for Windows also advertises these memory types. + */ + device->memory.type_count = 3; + device->memory.types[0] = (struct anv_memory_type) { + .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT, + .heapIndex = 0, + }; + device->memory.types[1] = (struct anv_memory_type) { + .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT | + VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | + VK_MEMORY_PROPERTY_HOST_COHERENT_BIT, + .heapIndex = 0, + }; + device->memory.types[2] = (struct anv_memory_type) { + .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT | + VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | + VK_MEMORY_PROPERTY_HOST_COHERENT_BIT | + VK_MEMORY_PROPERTY_HOST_CACHED_BIT, + .heapIndex = 0, + }; + } else { + /* The spec requires that we expose a host-visible, coherent memory + * type, but Atom GPUs don't share LLC. Thus we offer two memory types + * to give the application a choice between cached, but not coherent and + * coherent but uncached (WC though). + */ + device->memory.type_count = 2; + device->memory.types[0] = (struct anv_memory_type) { + .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT | + VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | + VK_MEMORY_PROPERTY_HOST_CACHED_BIT, + .heapIndex = 0, + }; + device->memory.types[1] = (struct anv_memory_type) { + .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT | + VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | + VK_MEMORY_PROPERTY_HOST_COHERENT_BIT, + .heapIndex = 0, + }; + } + + return VK_SUCCESS; +} + VkResult anv_i915_device_setup_context(struct anv_device *device, const VkDeviceCreateInfo *pCreateInfo, diff --git a/src/intel/vulkan/i915/anv_device.h b/src/intel/vulkan/i915/anv_device.h index af42c224161..5eecc0aa2d9 100644 --- a/src/intel/vulkan/i915/anv_device.h +++ b/src/intel/vulkan/i915/anv_device.h @@ -30,6 +30,8 @@ struct anv_physical_device; VkResult anv_i915_physical_device_get_parameters(struct anv_physical_device *device); +VkResult +anv_i915_physical_device_init_memory_types(struct anv_physical_device *device); VkResult anv_i915_device_setup_context(struct anv_device *device, diff --git a/src/intel/vulkan/xe/anv_device.c b/src/intel/vulkan/xe/anv_device.c index a5827d968ee..d839a54a4f4 100644 --- a/src/intel/vulkan/xe/anv_device.c +++ b/src/intel/vulkan/xe/anv_device.c @@ -118,6 +118,60 @@ anv_xe_physical_device_get_parameters(struct anv_physical_device *device) return VK_SUCCESS; } +VkResult +anv_xe_physical_device_init_memory_types(struct anv_physical_device *device) +{ + if (anv_physical_device_has_vram(device)) { + device->memory.type_count = 3; + device->memory.types[0] = (struct anv_memory_type) { + .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT, + .heapIndex = 0, + }; + device->memory.types[1] = (struct anv_memory_type) { + .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | + VK_MEMORY_PROPERTY_HOST_COHERENT_BIT | + VK_MEMORY_PROPERTY_HOST_CACHED_BIT, + .heapIndex = 1, + }; + device->memory.types[2] = (struct anv_memory_type) { + .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT | + VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | + VK_MEMORY_PROPERTY_HOST_COHERENT_BIT, + /* This memory type either comes from heaps[0] if there is only + * mappable vram region, or from heaps[2] if there is both mappable & + * non-mappable vram regions. + */ + .heapIndex = device->vram_non_mappable.size > 0 ? 2 : 0, + }; + } else if (device->info.has_llc) { + /* Big core GPUs share LLC with the CPU and thus one memory type can be + * both cached and coherent at the same time. + * + * But some game engines can't handle single type well + * https://gitlab.freedesktop.org/mesa/mesa/-/issues/7360#note_1719438 + * + * TODO: But with current UAPI we can't change the mmap mode in Xe, so + * here only supporting two memory types. + */ + device->memory.type_count = 2; + device->memory.types[0] = (struct anv_memory_type) { + .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT, + .heapIndex = 0, + }; + device->memory.types[1] = (struct anv_memory_type) { + .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT | + VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | + VK_MEMORY_PROPERTY_HOST_COHERENT_BIT | + VK_MEMORY_PROPERTY_HOST_CACHED_BIT, + .heapIndex = 0, + }; + } else { + return vk_errorf(device, VK_ERROR_INITIALIZATION_FAILED, + "No memory heaps types set for non llc devices yet on Xe"); + } + return VK_SUCCESS; +} + VkResult anv_xe_device_check_status(struct vk_device *vk_device) { diff --git a/src/intel/vulkan/xe/anv_device.h b/src/intel/vulkan/xe/anv_device.h index 669d5639c99..7cb5568b256 100644 --- a/src/intel/vulkan/xe/anv_device.h +++ b/src/intel/vulkan/xe/anv_device.h @@ -38,5 +38,8 @@ VkResult anv_xe_device_check_status(struct vk_device *vk_device); VkResult anv_xe_physical_device_get_parameters(struct anv_physical_device *device); +VkResult +anv_xe_physical_device_init_memory_types(struct anv_physical_device *device); + enum drm_sched_priority anv_vk_priority_to_drm_sched_priority(VkQueueGlobalPriorityKHR vk_priority);