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radv: add a radv_compiler_info object
This object contains everything needed for compiling AMD binaries from SPIR-V to assembly. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40992>
This commit is contained in:
Samuel Pitoiset
Marge Bot
parent
6e86d2877b
commit
4a91fd8bab
3 changed files with 233 additions and 0 deletions
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@ -69,6 +69,8 @@ typedef void *drmDevicePtr;
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#include "ac_descriptors.h"
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#include "ac_formats.h"
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#include "aco_interface.h"
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static bool
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radv_trap_handler_enabled()
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{
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@ -1096,6 +1098,144 @@ radv_device_init_msaa(struct radv_device *device)
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radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
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}
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static bool
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radv_device_is_cache_disabled(const struct radv_device *device)
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{
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const struct radv_physical_device *pdev = radv_device_physical(device);
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const struct radv_instance *instance = radv_physical_device_instance(pdev);
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/* The buffer address used for debug printf is hardcoded. */
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if (device->debug_nir.printf.buffer_addr)
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return true;
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/* The buffer address used for validating VAs is hardcoded. */
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if (device->debug_nir.valid_va.buffer_addr)
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return true;
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/* Pipeline caches can be disabled with RADV_DEBUG=nocache, with MESA_GLSL_CACHE_DISABLE=1 and
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* when ACO_DEBUG is used. MESA_GLSL_CACHE_DISABLE is done elsewhere.
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*/
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if ((instance->debug_flags & RADV_DEBUG_NO_CACHE) || (pdev->use_llvm ? 0 : aco_get_codegen_flags()))
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return true;
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return false;
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}
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static void
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radv_device_init_compiler_info(struct radv_device *device)
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{
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const struct radv_physical_device *pdev = radv_device_physical(device);
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struct radv_instance *instance = radv_physical_device_instance(pdev);
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VkShaderStageFlags dump_shaders = 0;
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if (instance->debug_flags & RADV_DEBUG_DUMP_VS)
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dump_shaders |= VK_SHADER_STAGE_VERTEX_BIT;
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if (instance->debug_flags & RADV_DEBUG_DUMP_TCS)
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dump_shaders |= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT;
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if (instance->debug_flags & RADV_DEBUG_DUMP_TES)
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dump_shaders |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
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if (instance->debug_flags & RADV_DEBUG_DUMP_GS)
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dump_shaders |= VK_SHADER_STAGE_GEOMETRY_BIT;
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if (instance->debug_flags & RADV_DEBUG_DUMP_PS)
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dump_shaders |= VK_SHADER_STAGE_FRAGMENT_BIT;
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if (instance->debug_flags & RADV_DEBUG_DUMP_TASK)
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dump_shaders |= VK_SHADER_STAGE_TASK_BIT_EXT;
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if (instance->debug_flags & RADV_DEBUG_DUMP_MESH)
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dump_shaders |= VK_SHADER_STAGE_MESH_BIT_EXT;
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if (instance->debug_flags & RADV_DEBUG_DUMP_CS)
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dump_shaders |= VK_SHADER_STAGE_COMPUTE_BIT | RADV_RT_STAGE_BITS;
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struct radv_compiler_info info = {
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/* Hardware info */
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.ac = &pdev->info.compiler_info,
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.hw =
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{
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.family = pdev->info.family,
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.address32_hi = pdev->info.address32_hi,
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.rbplus_allowed = pdev->info.rbplus_allowed,
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.mesh_fast_launch_2 = pdev->info.mesh_fast_launch_2,
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.has_dedicated_vram = pdev->info.has_dedicated_vram,
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.has_cs_regalloc_hang_bug = pdev->info.has_cs_regalloc_hang_bug,
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.lds_size_per_workgroup = pdev->info.lds_size_per_workgroup,
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},
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/* Debug/tracing */
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.debug =
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{
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.dump_spirv = !!(instance->debug_flags & RADV_DEBUG_DUMP_SPIRV),
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.dump_backend_ir = !!(instance->debug_flags & RADV_DEBUG_DUMP_BACKEND_IR),
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.dump_preopt_ir = !!(instance->debug_flags & RADV_DEBUG_DUMP_PREOPT_IR),
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.dump_nir = !!(instance->debug_flags & RADV_DEBUG_DUMP_NIR),
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.dump_asm = !!(instance->debug_flags & RADV_DEBUG_DUMP_ASM),
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.dump_meta_shaders = !!(instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS),
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.dump_shader_stats = !!(instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS),
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.nir_debug_info = !!(instance->debug_flags & RADV_DEBUG_NIR_DEBUG_INFO),
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.dump_shaders = dump_shaders,
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.check_ir = !!(instance->debug_flags & RADV_DEBUG_CHECKIR),
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.printf_enabled = !!device->debug_nir.printf.buffer_addr,
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.use_llvm = pdev->use_llvm,
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.trap_enabled = !!device->trap_handler_shader,
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.trap_excp_flags = instance->trap_excp_flags,
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.debug_report = &instance->vk.debug_report,
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.debug_nir = &device->debug_nir,
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.shader_dump_mtx = &instance->shader_dump_mtx,
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.keep_shader_info = device->keep_shader_info,
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.capture_shaders = (instance->debug_flags & RADV_DEBUG_DUMP_SHADERS) || device->keep_shader_info,
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/* Capture shader statistics when RGP is enabled to correlate shader hashes with Fossilize. */
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.capture_shader_stats = (instance->debug_flags & (RADV_DEBUG_DUMP_SHADER_STATS | RADV_DEBUG_PSO_HISTORY)) ||
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device->keep_shader_info || (instance->vk.trace_mode & RADV_TRACE_MODE_RGP),
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},
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.rra_trace = &device->rra_trace,
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/* Cache */
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.cache_disabled = radv_device_is_cache_disabled(device),
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.enable_nir_cache = !!(instance->debug_flags & RADV_PERFTEST_NIR_CACHE),
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.mem_cache = device->mem_cache,
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.cache_key = &pdev->cache_key,
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.override_graphics_shader_version = instance->drirc.misc.override_graphics_shader_version,
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.override_ray_tracing_shader_version = instance->drirc.misc.override_ray_tracing_shader_version,
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.override_compute_shader_version = instance->drirc.misc.override_compute_shader_version,
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/* Descriptors */
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.sampled_image_desc_size = radv_get_sampled_image_desc_size(pdev),
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.combined_image_sampler_desc_size = radv_get_combined_image_sampler_desc_size(pdev),
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.combined_image_sampler_offset = radv_get_combined_image_sampler_offset(pdev),
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.sampler_descriptor_size = pdev->vk.properties.samplerDescriptorSize,
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.sampler_descriptor_alignment = pdev->vk.properties.samplerDescriptorAlignment,
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.image_descriptor_size = pdev->vk.properties.imageDescriptorSize,
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.image_descriptor_alignment = pdev->vk.properties.imageDescriptorAlignment,
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.buffer_descriptor_size = pdev->vk.properties.bufferDescriptorSize,
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.buffer_descriptor_alignment = pdev->vk.properties.bufferDescriptorAlignment,
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/* Shader features */
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.use_ngg = pdev->use_ngg,
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.use_ngg_streamout = pdev->use_ngg_streamout,
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.load_grid_size_from_user_sgpr = device->load_grid_size_from_user_sgpr,
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.emulate_ngg_gs_query_pipeline_stat = pdev->emulate_ngg_gs_query_pipeline_stat,
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.primitives_generated_query = device->cache_key.primitives_generated_query,
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.mesh_shader_queries = device->cache_key.mesh_shader_queries,
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.image_2d_view_of_3d = device->cache_key.image_2d_view_of_3d,
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.use_fmask = pdev->use_fmask,
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.smooth_lines = device->vk.enabled_features.smoothLines,
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.force_vrs_enabled = device->force_vrs_enabled,
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.robust_buffer_access =
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(device->vk.enabled_features.robustBufferAccess2 || device->vk.enabled_features.robustBufferAccess),
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.force_aniso = device->force_aniso,
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/* Wave/subgroup sizes */
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.subgroup_size = device->vk.physical->properties.subgroupSize,
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.min_subgroup_size = device->vk.physical->properties.minSubgroupSize,
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.max_subgroup_size = device->vk.physical->properties.maxSubgroupSize,
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.ge_wave_size = pdev->ge_wave_size,
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.ps_wave_size = pdev->ps_wave_size,
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.cs_wave_size = pdev->cs_wave_size,
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.rt_wave_size = pdev->rt_wave_size,
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/* NIR/SPIR-V */
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.spirv_caps = vk_physical_device_get_spirv_capabilities(device->vk.physical),
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};
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for (uint32_t s = 0; s < MESA_VULKAN_SHADER_STAGES; s++)
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info.nir_options[s] = pdev->nir_options[s];
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device->compiler_info = info;
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}
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static void
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radv_destroy_device(struct radv_device *device, const VkAllocationCallbacks *pAllocator)
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{
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@ -1387,6 +1527,8 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr
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goto fail;
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}
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radv_device_init_compiler_info(device);
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if (device->vk.enabled_features.vertexInputDynamicState || device->vk.enabled_features.graphicsPipelineLibrary ||
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device->vk.enabled_features.shaderObject) {
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result = radv_device_init_vs_prologs(device);
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@ -326,6 +326,8 @@ struct radv_device {
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simple_mtx_t blit_queue_mtx;
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struct radv_address_binding_tracker *addr_binding_tracker;
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struct radv_compiler_info compiler_info;
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};
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VK_DEFINE_HANDLE_CASTS(radv_device, vk.base, VkDevice, VK_OBJECT_TYPE_DEVICE)
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@ -24,6 +24,9 @@
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#include "vk_nir_lower_descriptor_heaps.h"
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#include "vk_pipeline_cache.h"
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#include "nir/nir_shader_compiler_options.h"
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#include "spirv/spirv_info.h"
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#include "aco_shader_info.h"
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struct radv_physical_device;
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@ -507,6 +510,92 @@ struct radv_shader_dma_submission {
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uint64_t seq;
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};
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struct radv_compiler_info {
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/* Hardware info */
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const struct ac_compiler_info *ac;
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struct {
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uint32_t family;
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uint32_t address32_hi;
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bool rbplus_allowed;
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bool mesh_fast_launch_2;
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bool has_dedicated_vram;
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bool has_cs_regalloc_hang_bug;
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uint32_t lds_size_per_workgroup;
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} hw;
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/* Debug/tracing */
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struct {
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bool dump_spirv;
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bool dump_backend_ir;
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bool dump_preopt_ir;
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bool dump_nir;
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bool dump_asm;
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bool dump_meta_shaders;
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bool dump_shader_stats;
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bool nir_debug_info;
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VkShaderStageFlags dump_shaders;
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bool check_ir;
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bool printf_enabled;
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bool use_llvm;
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bool trap_enabled;
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uint64_t trap_excp_flags;
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struct vk_debug_report *debug_report;
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struct radv_debug_nir *debug_nir;
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simple_mtx_t *shader_dump_mtx;
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bool keep_shader_info;
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bool capture_shaders;
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bool capture_shader_stats;
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} debug;
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struct radv_rra_trace_data *rra_trace;
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/* Cache */
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bool cache_disabled;
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bool enable_nir_cache;
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struct vk_pipeline_cache *mem_cache;
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const struct radv_physical_device_cache_key *cache_key;
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uint8_t override_compute_shader_version;
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uint8_t override_graphics_shader_version;
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uint8_t override_ray_tracing_shader_version;
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/* Shader features */
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uint8_t sampled_image_desc_size;
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uint8_t combined_image_sampler_desc_size;
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uint8_t combined_image_sampler_offset;
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uint32_t sampler_descriptor_size;
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uint32_t sampler_descriptor_alignment;
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uint32_t image_descriptor_size;
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uint32_t image_descriptor_alignment;
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uint32_t buffer_descriptor_size;
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uint32_t buffer_descriptor_alignment;
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bool use_ngg;
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bool use_ngg_streamout;
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bool load_grid_size_from_user_sgpr;
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bool emulate_ngg_gs_query_pipeline_stat;
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bool primitives_generated_query;
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bool mesh_shader_queries;
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bool image_2d_view_of_3d;
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bool use_fmask;
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bool smooth_lines;
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bool force_vrs_enabled;
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bool robust_buffer_access; /* Only used by LLVM. */
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int force_aniso;
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/* Wave/subgroup sizes */
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uint32_t subgroup_size;
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uint32_t min_subgroup_size;
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uint32_t max_subgroup_size;
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uint8_t ge_wave_size;
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uint8_t ps_wave_size;
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uint8_t cs_wave_size;
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uint8_t rt_wave_size;
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/* NIR/SPIR-V */
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struct spirv_capabilities spirv_caps;
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nir_shader_compiler_options nir_options[MESA_VULKAN_SHADER_STAGES];
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};
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struct radv_shader_stage;
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void radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively);
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