From 4a91fd8babce0e344dd15120d8428d74600ea39b Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 25 Feb 2026 11:39:56 +0100 Subject: [PATCH] radv: add a radv_compiler_info object This object contains everything needed for compiling AMD binaries from SPIR-V to assembly. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_device.c | 142 +++++++++++++++++++++++++++++++++++ src/amd/vulkan/radv_device.h | 2 + src/amd/vulkan/radv_shader.h | 89 ++++++++++++++++++++++ 3 files changed, 233 insertions(+) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index fa9cfdee063..c224b05e313 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -69,6 +69,8 @@ typedef void *drmDevicePtr; #include "ac_descriptors.h" #include "ac_formats.h" +#include "aco_interface.h" + static bool radv_trap_handler_enabled() { @@ -1096,6 +1098,144 @@ radv_device_init_msaa(struct radv_device *device) radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]); } +static bool +radv_device_is_cache_disabled(const struct radv_device *device) +{ + const struct radv_physical_device *pdev = radv_device_physical(device); + const struct radv_instance *instance = radv_physical_device_instance(pdev); + + /* The buffer address used for debug printf is hardcoded. */ + if (device->debug_nir.printf.buffer_addr) + return true; + + /* The buffer address used for validating VAs is hardcoded. */ + if (device->debug_nir.valid_va.buffer_addr) + return true; + + /* Pipeline caches can be disabled with RADV_DEBUG=nocache, with MESA_GLSL_CACHE_DISABLE=1 and + * when ACO_DEBUG is used. MESA_GLSL_CACHE_DISABLE is done elsewhere. + */ + if ((instance->debug_flags & RADV_DEBUG_NO_CACHE) || (pdev->use_llvm ? 0 : aco_get_codegen_flags())) + return true; + + return false; +} + +static void +radv_device_init_compiler_info(struct radv_device *device) +{ + const struct radv_physical_device *pdev = radv_device_physical(device); + struct radv_instance *instance = radv_physical_device_instance(pdev); + + VkShaderStageFlags dump_shaders = 0; + + if (instance->debug_flags & RADV_DEBUG_DUMP_VS) + dump_shaders |= VK_SHADER_STAGE_VERTEX_BIT; + if (instance->debug_flags & RADV_DEBUG_DUMP_TCS) + dump_shaders |= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT; + if (instance->debug_flags & RADV_DEBUG_DUMP_TES) + dump_shaders |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT; + if (instance->debug_flags & RADV_DEBUG_DUMP_GS) + dump_shaders |= VK_SHADER_STAGE_GEOMETRY_BIT; + if (instance->debug_flags & RADV_DEBUG_DUMP_PS) + dump_shaders |= VK_SHADER_STAGE_FRAGMENT_BIT; + if (instance->debug_flags & RADV_DEBUG_DUMP_TASK) + dump_shaders |= VK_SHADER_STAGE_TASK_BIT_EXT; + if (instance->debug_flags & RADV_DEBUG_DUMP_MESH) + dump_shaders |= VK_SHADER_STAGE_MESH_BIT_EXT; + if (instance->debug_flags & RADV_DEBUG_DUMP_CS) + dump_shaders |= VK_SHADER_STAGE_COMPUTE_BIT | RADV_RT_STAGE_BITS; + + struct radv_compiler_info info = { + /* Hardware info */ + .ac = &pdev->info.compiler_info, + .hw = + { + .family = pdev->info.family, + .address32_hi = pdev->info.address32_hi, + .rbplus_allowed = pdev->info.rbplus_allowed, + .mesh_fast_launch_2 = pdev->info.mesh_fast_launch_2, + .has_dedicated_vram = pdev->info.has_dedicated_vram, + .has_cs_regalloc_hang_bug = pdev->info.has_cs_regalloc_hang_bug, + .lds_size_per_workgroup = pdev->info.lds_size_per_workgroup, + }, + /* Debug/tracing */ + .debug = + { + .dump_spirv = !!(instance->debug_flags & RADV_DEBUG_DUMP_SPIRV), + .dump_backend_ir = !!(instance->debug_flags & RADV_DEBUG_DUMP_BACKEND_IR), + .dump_preopt_ir = !!(instance->debug_flags & RADV_DEBUG_DUMP_PREOPT_IR), + .dump_nir = !!(instance->debug_flags & RADV_DEBUG_DUMP_NIR), + .dump_asm = !!(instance->debug_flags & RADV_DEBUG_DUMP_ASM), + .dump_meta_shaders = !!(instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS), + .dump_shader_stats = !!(instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS), + .nir_debug_info = !!(instance->debug_flags & RADV_DEBUG_NIR_DEBUG_INFO), + .dump_shaders = dump_shaders, + .check_ir = !!(instance->debug_flags & RADV_DEBUG_CHECKIR), + .printf_enabled = !!device->debug_nir.printf.buffer_addr, + .use_llvm = pdev->use_llvm, + .trap_enabled = !!device->trap_handler_shader, + .trap_excp_flags = instance->trap_excp_flags, + .debug_report = &instance->vk.debug_report, + .debug_nir = &device->debug_nir, + .shader_dump_mtx = &instance->shader_dump_mtx, + .keep_shader_info = device->keep_shader_info, + .capture_shaders = (instance->debug_flags & RADV_DEBUG_DUMP_SHADERS) || device->keep_shader_info, + /* Capture shader statistics when RGP is enabled to correlate shader hashes with Fossilize. */ + .capture_shader_stats = (instance->debug_flags & (RADV_DEBUG_DUMP_SHADER_STATS | RADV_DEBUG_PSO_HISTORY)) || + device->keep_shader_info || (instance->vk.trace_mode & RADV_TRACE_MODE_RGP), + }, + .rra_trace = &device->rra_trace, + /* Cache */ + .cache_disabled = radv_device_is_cache_disabled(device), + .enable_nir_cache = !!(instance->debug_flags & RADV_PERFTEST_NIR_CACHE), + .mem_cache = device->mem_cache, + .cache_key = &pdev->cache_key, + .override_graphics_shader_version = instance->drirc.misc.override_graphics_shader_version, + .override_ray_tracing_shader_version = instance->drirc.misc.override_ray_tracing_shader_version, + .override_compute_shader_version = instance->drirc.misc.override_compute_shader_version, + /* Descriptors */ + .sampled_image_desc_size = radv_get_sampled_image_desc_size(pdev), + .combined_image_sampler_desc_size = radv_get_combined_image_sampler_desc_size(pdev), + .combined_image_sampler_offset = radv_get_combined_image_sampler_offset(pdev), + .sampler_descriptor_size = pdev->vk.properties.samplerDescriptorSize, + .sampler_descriptor_alignment = pdev->vk.properties.samplerDescriptorAlignment, + .image_descriptor_size = pdev->vk.properties.imageDescriptorSize, + .image_descriptor_alignment = pdev->vk.properties.imageDescriptorAlignment, + .buffer_descriptor_size = pdev->vk.properties.bufferDescriptorSize, + .buffer_descriptor_alignment = pdev->vk.properties.bufferDescriptorAlignment, + /* Shader features */ + .use_ngg = pdev->use_ngg, + .use_ngg_streamout = pdev->use_ngg_streamout, + .load_grid_size_from_user_sgpr = device->load_grid_size_from_user_sgpr, + .emulate_ngg_gs_query_pipeline_stat = pdev->emulate_ngg_gs_query_pipeline_stat, + .primitives_generated_query = device->cache_key.primitives_generated_query, + .mesh_shader_queries = device->cache_key.mesh_shader_queries, + .image_2d_view_of_3d = device->cache_key.image_2d_view_of_3d, + .use_fmask = pdev->use_fmask, + .smooth_lines = device->vk.enabled_features.smoothLines, + .force_vrs_enabled = device->force_vrs_enabled, + .robust_buffer_access = + (device->vk.enabled_features.robustBufferAccess2 || device->vk.enabled_features.robustBufferAccess), + .force_aniso = device->force_aniso, + /* Wave/subgroup sizes */ + .subgroup_size = device->vk.physical->properties.subgroupSize, + .min_subgroup_size = device->vk.physical->properties.minSubgroupSize, + .max_subgroup_size = device->vk.physical->properties.maxSubgroupSize, + .ge_wave_size = pdev->ge_wave_size, + .ps_wave_size = pdev->ps_wave_size, + .cs_wave_size = pdev->cs_wave_size, + .rt_wave_size = pdev->rt_wave_size, + /* NIR/SPIR-V */ + .spirv_caps = vk_physical_device_get_spirv_capabilities(device->vk.physical), + }; + + for (uint32_t s = 0; s < MESA_VULKAN_SHADER_STAGES; s++) + info.nir_options[s] = pdev->nir_options[s]; + + device->compiler_info = info; +} + static void radv_destroy_device(struct radv_device *device, const VkAllocationCallbacks *pAllocator) { @@ -1387,6 +1527,8 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr goto fail; } + radv_device_init_compiler_info(device); + if (device->vk.enabled_features.vertexInputDynamicState || device->vk.enabled_features.graphicsPipelineLibrary || device->vk.enabled_features.shaderObject) { result = radv_device_init_vs_prologs(device); diff --git a/src/amd/vulkan/radv_device.h b/src/amd/vulkan/radv_device.h index 4cd4015d15b..f90be9aab7d 100644 --- a/src/amd/vulkan/radv_device.h +++ b/src/amd/vulkan/radv_device.h @@ -326,6 +326,8 @@ struct radv_device { simple_mtx_t blit_queue_mtx; struct radv_address_binding_tracker *addr_binding_tracker; + + struct radv_compiler_info compiler_info; }; VK_DEFINE_HANDLE_CASTS(radv_device, vk.base, VkDevice, VK_OBJECT_TYPE_DEVICE) diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 65fa47c3a71..28f37faa6bd 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -24,6 +24,9 @@ #include "vk_nir_lower_descriptor_heaps.h" #include "vk_pipeline_cache.h" +#include "nir/nir_shader_compiler_options.h" +#include "spirv/spirv_info.h" + #include "aco_shader_info.h" struct radv_physical_device; @@ -507,6 +510,92 @@ struct radv_shader_dma_submission { uint64_t seq; }; +struct radv_compiler_info { + /* Hardware info */ + const struct ac_compiler_info *ac; + + struct { + uint32_t family; + uint32_t address32_hi; + bool rbplus_allowed; + bool mesh_fast_launch_2; + bool has_dedicated_vram; + bool has_cs_regalloc_hang_bug; + uint32_t lds_size_per_workgroup; + } hw; + + /* Debug/tracing */ + struct { + bool dump_spirv; + bool dump_backend_ir; + bool dump_preopt_ir; + bool dump_nir; + bool dump_asm; + bool dump_meta_shaders; + bool dump_shader_stats; + bool nir_debug_info; + VkShaderStageFlags dump_shaders; + bool check_ir; + bool printf_enabled; + bool use_llvm; + bool trap_enabled; + uint64_t trap_excp_flags; + struct vk_debug_report *debug_report; + struct radv_debug_nir *debug_nir; + simple_mtx_t *shader_dump_mtx; + bool keep_shader_info; + bool capture_shaders; + bool capture_shader_stats; + } debug; + + struct radv_rra_trace_data *rra_trace; + + /* Cache */ + bool cache_disabled; + bool enable_nir_cache; + struct vk_pipeline_cache *mem_cache; + const struct radv_physical_device_cache_key *cache_key; + uint8_t override_compute_shader_version; + uint8_t override_graphics_shader_version; + uint8_t override_ray_tracing_shader_version; + + /* Shader features */ + uint8_t sampled_image_desc_size; + uint8_t combined_image_sampler_desc_size; + uint8_t combined_image_sampler_offset; + uint32_t sampler_descriptor_size; + uint32_t sampler_descriptor_alignment; + uint32_t image_descriptor_size; + uint32_t image_descriptor_alignment; + uint32_t buffer_descriptor_size; + uint32_t buffer_descriptor_alignment; + bool use_ngg; + bool use_ngg_streamout; + bool load_grid_size_from_user_sgpr; + bool emulate_ngg_gs_query_pipeline_stat; + bool primitives_generated_query; + bool mesh_shader_queries; + bool image_2d_view_of_3d; + bool use_fmask; + bool smooth_lines; + bool force_vrs_enabled; + bool robust_buffer_access; /* Only used by LLVM. */ + int force_aniso; + + /* Wave/subgroup sizes */ + uint32_t subgroup_size; + uint32_t min_subgroup_size; + uint32_t max_subgroup_size; + uint8_t ge_wave_size; + uint8_t ps_wave_size; + uint8_t cs_wave_size; + uint8_t rt_wave_size; + + /* NIR/SPIR-V */ + struct spirv_capabilities spirv_caps; + nir_shader_compiler_options nir_options[MESA_VULKAN_SHADER_STAGES]; +}; + struct radv_shader_stage; void radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively);