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util: fix (re-enable) L3 cache pinning
cores_per_L3 was uninitialized, so it was always disabled.
Remove the variable and do it differently.
Fixes: 11d2db17c5 - util: rework AMD cpu L3 cache affinity code.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10526>
This commit is contained in:
parent
9b58e31f2d
commit
48d2ac4e88
4 changed files with 4 additions and 4 deletions
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@ -216,7 +216,7 @@ _mesa_glthread_flush_batch(struct gl_context *ctx)
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/* Pin threads regularly to the same Zen CCX that the main thread is
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/* Pin threads regularly to the same Zen CCX that the main thread is
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* running on. The main thread can move between CCXs.
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* running on. The main thread can move between CCXs.
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*/
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*/
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if (util_get_cpu_caps()->nr_cpus != util_get_cpu_caps()->cores_per_L3 &&
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if (util_get_cpu_caps()->num_L3_caches > 1 &&
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/* driver support */
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/* driver support */
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ctx->Driver.PinDriverToL3Cache &&
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ctx->Driver.PinDriverToL3Cache &&
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++glthread->pin_thread_counter % 128 == 0) {
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++glthread->pin_thread_counter % 128 == 0) {
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@ -847,7 +847,9 @@ st_create_context_priv(struct gl_context *ctx, struct pipe_context *pipe,
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!st->lower_ucp;
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!st->lower_ucp;
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st->shader_has_one_variant[MESA_SHADER_COMPUTE] = st->has_shareable_shaders;
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st->shader_has_one_variant[MESA_SHADER_COMPUTE] = st->has_shareable_shaders;
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if (util_get_cpu_caps()->cores_per_L3 == util_get_cpu_caps()->nr_cpus ||
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util_cpu_detect();
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if (util_get_cpu_caps()->num_L3_caches == 1 ||
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!st->pipe->set_context_param)
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!st->pipe->set_context_param)
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st->pin_thread_counter = ST_L3_PINNING_DISABLED;
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st->pin_thread_counter = ST_L3_PINNING_DISABLED;
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@ -435,7 +435,6 @@ static void
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get_cpu_topology(void)
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get_cpu_topology(void)
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{
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{
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/* Default. This is OK if L3 is not present or there is only one. */
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/* Default. This is OK if L3 is not present or there is only one. */
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util_cpu_caps.cores_per_L3 = util_cpu_caps.nr_cpus;
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util_cpu_caps.num_L3_caches = 1;
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util_cpu_caps.num_L3_caches = 1;
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memset(util_cpu_caps.cpu_to_L3, 0xff, sizeof(util_cpu_caps.cpu_to_L3));
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memset(util_cpu_caps.cpu_to_L3, 0xff, sizeof(util_cpu_caps.cpu_to_L3));
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@ -97,7 +97,6 @@ struct util_cpu_caps_t {
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unsigned has_avx512vbmi:1;
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unsigned has_avx512vbmi:1;
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unsigned num_L3_caches;
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unsigned num_L3_caches;
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unsigned cores_per_L3;
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unsigned num_cpu_mask_bits;
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unsigned num_cpu_mask_bits;
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uint16_t cpu_to_L3[UTIL_MAX_CPUS];
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uint16_t cpu_to_L3[UTIL_MAX_CPUS];
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