From 48d2ac4e8852a4e7e0efba27799bb40d540b2f09 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 28 Apr 2021 21:27:02 -0400 Subject: [PATCH] util: fix (re-enable) L3 cache pinning cores_per_L3 was uninitialized, so it was always disabled. Remove the variable and do it differently. Fixes: 11d2db17c52 - util: rework AMD cpu L3 cache affinity code. Reviewed-by: Dave Airlie Part-of: --- src/mesa/main/glthread.c | 2 +- src/mesa/state_tracker/st_context.c | 4 +++- src/util/u_cpu_detect.c | 1 - src/util/u_cpu_detect.h | 1 - 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/main/glthread.c b/src/mesa/main/glthread.c index ace921333b3..ed619f5806c 100644 --- a/src/mesa/main/glthread.c +++ b/src/mesa/main/glthread.c @@ -216,7 +216,7 @@ _mesa_glthread_flush_batch(struct gl_context *ctx) /* Pin threads regularly to the same Zen CCX that the main thread is * running on. The main thread can move between CCXs. */ - if (util_get_cpu_caps()->nr_cpus != util_get_cpu_caps()->cores_per_L3 && + if (util_get_cpu_caps()->num_L3_caches > 1 && /* driver support */ ctx->Driver.PinDriverToL3Cache && ++glthread->pin_thread_counter % 128 == 0) { diff --git a/src/mesa/state_tracker/st_context.c b/src/mesa/state_tracker/st_context.c index 63f8c84c300..9f3b861299a 100644 --- a/src/mesa/state_tracker/st_context.c +++ b/src/mesa/state_tracker/st_context.c @@ -847,7 +847,9 @@ st_create_context_priv(struct gl_context *ctx, struct pipe_context *pipe, !st->lower_ucp; st->shader_has_one_variant[MESA_SHADER_COMPUTE] = st->has_shareable_shaders; - if (util_get_cpu_caps()->cores_per_L3 == util_get_cpu_caps()->nr_cpus || + util_cpu_detect(); + + if (util_get_cpu_caps()->num_L3_caches == 1 || !st->pipe->set_context_param) st->pin_thread_counter = ST_L3_PINNING_DISABLED; diff --git a/src/util/u_cpu_detect.c b/src/util/u_cpu_detect.c index fdb403a3593..ea066b96d8a 100644 --- a/src/util/u_cpu_detect.c +++ b/src/util/u_cpu_detect.c @@ -435,7 +435,6 @@ static void get_cpu_topology(void) { /* Default. This is OK if L3 is not present or there is only one. */ - util_cpu_caps.cores_per_L3 = util_cpu_caps.nr_cpus; util_cpu_caps.num_L3_caches = 1; memset(util_cpu_caps.cpu_to_L3, 0xff, sizeof(util_cpu_caps.cpu_to_L3)); diff --git a/src/util/u_cpu_detect.h b/src/util/u_cpu_detect.h index 1c7239b2ec7..73271ef3bc8 100644 --- a/src/util/u_cpu_detect.h +++ b/src/util/u_cpu_detect.h @@ -97,7 +97,6 @@ struct util_cpu_caps_t { unsigned has_avx512vbmi:1; unsigned num_L3_caches; - unsigned cores_per_L3; unsigned num_cpu_mask_bits; uint16_t cpu_to_L3[UTIL_MAX_CPUS];