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brw: Move PLN/LINE normalization
Add validation for Source 0 and move the normalization into the code producing the instruction. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38877>
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3 changed files with 13 additions and 16 deletions
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@ -923,19 +923,7 @@ ALU2(AVG)
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ALU2(ADD)
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ALU2(SRND)
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ALU2(LINE)
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brw_eu_inst *
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brw_PLN(struct brw_codegen *p, struct brw_reg dest,
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struct brw_reg src0, struct brw_reg src1)
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{
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src0.vstride = BRW_VERTICAL_STRIDE_0;
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src0.width = BRW_WIDTH_1;
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src0.hstride = BRW_HORIZONTAL_STRIDE_0;
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src1.vstride = BRW_VERTICAL_STRIDE_8;
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src1.width = BRW_WIDTH_8;
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src1.hstride = BRW_HORIZONTAL_STRIDE_1;
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return brw_alu2(p, BRW_OPCODE_PLN, dest, src0, src1);
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}
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ALU2(PLN)
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brw_eu_inst *
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brw_DPAS(struct brw_codegen *p, enum gfx12_systolic_depth sdepth,
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@ -2276,9 +2276,10 @@ instruction_restrictions(const struct brw_isa_info *isa,
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"ADD can't mix float and non-float sources.");
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}
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if (inst->opcode == BRW_OPCODE_LINE) {
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if (inst->opcode == BRW_OPCODE_LINE ||
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inst->opcode == BRW_OPCODE_PLN) {
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ERROR_IF(!src_has_scalar_region(inst, 0),
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"LINE source 0 must be a scalar.");
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"LINE/PLN source 0 must be a scalar.");
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}
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}
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@ -4239,13 +4239,21 @@ brw_from_nir_emit_fs_intrinsic(nir_to_brw_state &ntb,
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dst_xy = s.delta_xy[bary];
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}
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/* Force valid linear stride for src1 of PLN. See
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* b14313e4529 ("i965/fs: Manually set source regioning on
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* PLN instructions.") for details.
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*/
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dst_xy.vstride = BRW_VERTICAL_STRIDE_8;
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dst_xy.width = BRW_WIDTH_8;
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dst_xy.hstride = BRW_HORIZONTAL_STRIDE_1;
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for (unsigned int i = 0; i < instr->num_components; i++) {
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brw_reg interp =
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brw_interp_reg(bld, nir_intrinsic_base(instr),
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nir_intrinsic_component(instr) + i, 0);
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interp.type = BRW_TYPE_F;
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dest.type = BRW_TYPE_F;
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assert(is_uniform(interp));
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bld.PLN(offset(dest, bld, i), interp, dst_xy);
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}
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break;
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