diff --git a/src/intel/compiler/brw/brw_eu_emit.c b/src/intel/compiler/brw/brw_eu_emit.c
index f6f0b73d513..9be3fcd74d7 100644
--- a/src/intel/compiler/brw/brw_eu_emit.c
+++ b/src/intel/compiler/brw/brw_eu_emit.c
@@ -923,19 +923,7 @@ ALU2(AVG)
 ALU2(ADD)
 ALU2(SRND)
 ALU2(LINE)
-
-brw_eu_inst *
-brw_PLN(struct brw_codegen *p, struct brw_reg dest,
-        struct brw_reg src0, struct brw_reg src1)
-{
-   src0.vstride = BRW_VERTICAL_STRIDE_0;
-   src0.width = BRW_WIDTH_1;
-   src0.hstride = BRW_HORIZONTAL_STRIDE_0;
-   src1.vstride = BRW_VERTICAL_STRIDE_8;
-   src1.width = BRW_WIDTH_8;
-   src1.hstride = BRW_HORIZONTAL_STRIDE_1;
-   return brw_alu2(p, BRW_OPCODE_PLN, dest, src0, src1);
-}
+ALU2(PLN)
 
 brw_eu_inst *
 brw_DPAS(struct brw_codegen *p, enum gfx12_systolic_depth sdepth,
diff --git a/src/intel/compiler/brw/brw_eu_validate.c b/src/intel/compiler/brw/brw_eu_validate.c
index 2ea38604ef2..574166c5197 100644
--- a/src/intel/compiler/brw/brw_eu_validate.c
+++ b/src/intel/compiler/brw/brw_eu_validate.c
@@ -2276,9 +2276,10 @@ instruction_restrictions(const struct brw_isa_info *isa,
                "ADD can't mix float and non-float sources.");
    }
 
-   if (inst->opcode == BRW_OPCODE_LINE) {
+   if (inst->opcode == BRW_OPCODE_LINE ||
+       inst->opcode == BRW_OPCODE_PLN) {
       ERROR_IF(!src_has_scalar_region(inst, 0),
-               "LINE source 0 must be a scalar.");
+               "LINE/PLN source 0 must be a scalar.");
    }
 }
 
diff --git a/src/intel/compiler/brw/brw_from_nir.cpp b/src/intel/compiler/brw/brw_from_nir.cpp
index 78a868021b9..d6b366841c8 100644
--- a/src/intel/compiler/brw/brw_from_nir.cpp
+++ b/src/intel/compiler/brw/brw_from_nir.cpp
@@ -4239,13 +4239,21 @@ brw_from_nir_emit_fs_intrinsic(nir_to_brw_state &ntb,
          dst_xy = s.delta_xy[bary];
       }
 
+      /* Force valid linear stride for src1 of PLN.  See
+       * b14313e4529 ("i965/fs: Manually set source regioning on
+       * PLN instructions.") for details.
+       */
+      dst_xy.vstride = BRW_VERTICAL_STRIDE_8;
+      dst_xy.width = BRW_WIDTH_8;
+      dst_xy.hstride = BRW_HORIZONTAL_STRIDE_1;
+
       for (unsigned int i = 0; i < instr->num_components; i++) {
          brw_reg interp =
             brw_interp_reg(bld, nir_intrinsic_base(instr),
                            nir_intrinsic_component(instr) + i, 0);
          interp.type = BRW_TYPE_F;
          dest.type = BRW_TYPE_F;
-
+         assert(is_uniform(interp));
          bld.PLN(offset(dest, bld, i), interp, dst_xy);
       }
       break;