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radv: remove an old FIXME about a possible bug with TC-compat HTILE

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I added this FIXME 2 years ago because it was unclear if it was
broken or not. Since, CTS coverage improved and the number of tests
with depth/stencil on the compute queue increased a lot. vkd3d-proton
also widely uses depth/stencil with GENERAL on GFX10+ and likely with
async compute as well. No issues so far.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4048
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20785>
This commit is contained in:
Samuel Pitoiset 2023-01-19 10:14:53 +01:00 • committed by Marge Bot
parent 1c82981bbe
commit 473732dfd1
1 changed files with 0 additions and 3 deletions
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3
src/amd/vulkan/radv_image.c
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@ -2298,9 +2298,6 @@ radv_layout_is_htile_compressed(const struct radv_device *device, const struct r
* depth pass because this allows compression and this reduces
* the number of decompressions from/to GENERAL.
*/
/* FIXME: Enabling TC-compat HTILE in GENERAL on the compute
* queue is likely broken for eg. depth/stencil copies.
*/
if (radv_image_is_tc_compat_htile(image) && queue_mask & (1u << RADV_QUEUE_GENERAL) &&
!device->instance->disable_tc_compat_htile_in_general) {
return true;