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anv: fix 3d state initialization

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We missed a couple of restriction leading to inconsistent 3d pipeline
state. It is mostly noticeable when doing a multiple sample dispatch
as the verify first 3d operation.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7531
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19867>
(cherry picked from commit 62f12c2dad)
This commit is contained in:
Lionel Landwerlin 2022-11-19 14:29:43 +02:00 • committed by Eric Engestrom
parent 73580de2e8
commit 46517e0b65
2 changed files with 21 additions and 2 deletions
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2
.pick_status.json
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@ -724,7 +724,7 @@
"description": "anv: fix 3d state initialization",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null
},

21
src/intel/vulkan/genX_state.c
View file

@ -299,7 +299,24 @@ init_render_queue_state(struct anv_queue *queue)
anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);
genX(emit_sample_pattern)(&batch, NULL);
/* SKL PRMs, Volume 2a: Command Reference: Instructions: 3DSTATE_WM_HZ_OP:
*
* "3DSTATE_RASTER if used must be programmed prior to using this
* packet."
*
* Emit this before 3DSTATE_WM_HZ_OP below.
*/
anv_batch_emit(&batch, GENX(3DSTATE_RASTER), rast);
/* SKL PRMs, Volume 2a: Command Reference: Instructions: 3DSTATE_WM_HZ_OP:
*
* "3DSTATE_MULTISAMPLE packet must be used prior to this packet to
* change the Number of Multisamples. This packet must not be used to
* change Number of Multisamples in a rendering sequence."
*
* Emit this before 3DSTATE_WM_HZ_OP below.
*/
genX(emit_multisample)(&batch, 1);
/* The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the
* section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer
@ -311,6 +328,8 @@ init_render_queue_state(struct anv_queue *queue)
*/
anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp);
genX(emit_sample_pattern)(&batch, NULL);
#if GFX_VER == 11
/* The default behavior of bit 5 "Headerless Message for Pre-emptable
* Contexts" in SAMPLER MODE register is set to 0, which means