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intel/brw: Delete SHADER_OPCODE_TXF_UMS

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Nothing seems to generate this anymore.  I guess we always use CMS.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27908>
This commit is contained in:
Kenneth Graunke 2024-02-29 23:51:39 -08:00 • committed by Marge Bot
parent 601ef12467
commit 45a5e4c0c4
7 changed files with 1 additions and 25 deletions
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2
src/intel/compiler/brw_eu_defines.h
View file

@ -301,8 +301,6 @@ enum opcode {
SHADER_OPCODE_TXF_CMS_W,
SHADER_OPCODE_TXF_CMS_W_LOGICAL,
SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL,
SHADER_OPCODE_TXF_UMS,
SHADER_OPCODE_TXF_UMS_LOGICAL,
SHADER_OPCODE_TXF_MCS,
SHADER_OPCODE_TXF_MCS_LOGICAL,
SHADER_OPCODE_LOD,

8
src/intel/compiler/brw_fs.cpp
View file

@ -243,7 +243,6 @@ fs_inst::is_control_source(unsigned arg) const
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_LZ:
case SHADER_OPCODE_TXF_CMS_W:
case SHADER_OPCODE_TXF_UMS:
case SHADER_OPCODE_TXF_MCS:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXL_LZ:
@ -284,7 +283,6 @@ fs_inst::is_payload(unsigned arg) const
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_LZ:
case SHADER_OPCODE_TXF_CMS_W:
case SHADER_OPCODE_TXF_UMS:
case SHADER_OPCODE_TXF_MCS:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXL_LZ:
@ -751,7 +749,6 @@ fs_inst::components_read(unsigned i) const
case FS_OPCODE_TXB_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
case SHADER_OPCODE_TXF_UMS_LOGICAL:
case SHADER_OPCODE_TXF_MCS_LOGICAL:
case SHADER_OPCODE_LOD_LOGICAL:
case SHADER_OPCODE_TG4_LOGICAL:
@ -968,7 +965,6 @@ fs_inst::size_read(int arg) const
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_LZ:
case SHADER_OPCODE_TXF_CMS_W:
case SHADER_OPCODE_TXF_UMS:
case SHADER_OPCODE_TXF_MCS:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXL_LZ:
@ -2381,10 +2377,6 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op)
return "txf_cms_w_logical";
case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
return "txf_cms_w_gfx12_logical";
case SHADER_OPCODE_TXF_UMS:
return "txf_ums";
case SHADER_OPCODE_TXF_UMS_LOGICAL:
return "txf_ums_logical";
case SHADER_OPCODE_TXF_MCS:
return "txf_mcs";
case SHADER_OPCODE_TXF_MCS_LOGICAL:

1
src/intel/compiler/brw_fs_copy_propagation.cpp
View file

@ -1170,7 +1170,6 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
case FS_OPCODE_TXB_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
case SHADER_OPCODE_TXF_UMS_LOGICAL:
case SHADER_OPCODE_TXF_MCS_LOGICAL:
case SHADER_OPCODE_LOD_LOGICAL:
case SHADER_OPCODE_TG4_BIAS_LOGICAL:

1
src/intel/compiler/brw_fs_cse.cpp
View file

@ -89,7 +89,6 @@ is_expression(const fs_visitor *v, const fs_inst *const inst)
case SHADER_OPCODE_TXS_LOGICAL:
case FS_OPCODE_TXB_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
case SHADER_OPCODE_TXF_UMS_LOGICAL:
case SHADER_OPCODE_TXF_MCS_LOGICAL:
case SHADER_OPCODE_LOD_LOGICAL:
case SHADER_OPCODE_TG4_LOGICAL:

1
src/intel/compiler/brw_fs_lower_simd_width.cpp
View file

@ -323,7 +323,6 @@ brw_fs_get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst)
return MIN2(16, inst->exec_size);
case SHADER_OPCODE_TEX_LOGICAL:
case SHADER_OPCODE_TXF_UMS_LOGICAL:
case SHADER_OPCODE_TXF_MCS_LOGICAL:
case SHADER_OPCODE_LOD_LOGICAL:
case SHADER_OPCODE_TG4_LOGICAL:

1
src/intel/compiler/brw_ir_performance.cpp
View file

@ -558,7 +558,6 @@ namespace {
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXL_LZ:
case SHADER_OPCODE_TXF_CMS_W:
case SHADER_OPCODE_TXF_UMS:
case SHADER_OPCODE_TXF_MCS:
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_LOD:

12
src/intel/compiler/brw_lower_logical_sends.cpp
View file

@ -609,9 +609,6 @@ sampler_msg_type(const intel_device_info *devinfo,
case SHADER_OPCODE_TXF_CMS_W:
assert(!has_min_lod);
return GFX9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
case SHADER_OPCODE_TXF_UMS:
assert(!has_min_lod);
return GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
case SHADER_OPCODE_TXF_MCS:
assert(!has_min_lod);
return GFX7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
@ -961,10 +958,8 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op,
break;
case SHADER_OPCODE_TXF_CMS_W:
case SHADER_OPCODE_TXF_UMS:
case SHADER_OPCODE_TXF_MCS:
if (op == SHADER_OPCODE_TXF_UMS ||
op == SHADER_OPCODE_TXF_CMS_W) {
if (op == SHADER_OPCODE_TXF_CMS_W) {
bld.MOV(retype(sources[length++], payload_unsigned_type), sample_index);
}
@ -1253,7 +1248,6 @@ get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo,
*/
if (op == SHADER_OPCODE_TXF_CMS_W ||
op == SHADER_OPCODE_TXF_UMS ||
op == SHADER_OPCODE_TXF_MCS ||
(op == FS_OPCODE_TXB && !inst->has_packed_lod_ai_src &&
devinfo->ver >= 20))
@ -2796,10 +2790,6 @@ brw_fs_lower_logical_sends(fs_visitor &s)
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_CMS_W);
break;
case SHADER_OPCODE_TXF_UMS_LOGICAL:
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_UMS);
break;
case SHADER_OPCODE_TXF_MCS_LOGICAL:
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_MCS);
break;