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intel/brw: Delete SHADER_OPCODE_TXF_CMS[_LOGICAL]

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We always use the wide variant (_W) on hardware this compiler supports.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27908>
This commit is contained in:
Kenneth Graunke 2024-02-29 23:48:25 -08:00 • committed by Marge Bot
parent 494eee1337
commit 601ef12467
7 changed files with 2 additions and 29 deletions
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2
src/intel/compiler/brw_eu_defines.h
View file

@ -298,8 +298,6 @@ enum opcode {
SHADER_OPCODE_TXS_LOGICAL,
FS_OPCODE_TXB,
FS_OPCODE_TXB_LOGICAL,
SHADER_OPCODE_TXF_CMS,
SHADER_OPCODE_TXF_CMS_LOGICAL,
SHADER_OPCODE_TXF_CMS_W,
SHADER_OPCODE_TXF_CMS_W_LOGICAL,
SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL,

9
src/intel/compiler/brw_fs.cpp
View file

@ -242,7 +242,6 @@ fs_inst::is_control_source(unsigned arg) const
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_LZ:
case SHADER_OPCODE_TXF_CMS:
case SHADER_OPCODE_TXF_CMS_W:
case SHADER_OPCODE_TXF_UMS:
case SHADER_OPCODE_TXF_MCS:
@ -284,7 +283,6 @@ fs_inst::is_payload(unsigned arg) const
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_LZ:
case SHADER_OPCODE_TXF_CMS:
case SHADER_OPCODE_TXF_CMS_W:
case SHADER_OPCODE_TXF_UMS:
case SHADER_OPCODE_TXF_MCS:
@ -751,7 +749,6 @@ fs_inst::components_read(unsigned i) const
case SHADER_OPCODE_TXS_LOGICAL:
case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
case FS_OPCODE_TXB_LOGICAL:
case SHADER_OPCODE_TXF_CMS_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
case SHADER_OPCODE_TXF_UMS_LOGICAL:
@ -970,7 +967,6 @@ fs_inst::size_read(int arg) const
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_LZ:
case SHADER_OPCODE_TXF_CMS:
case SHADER_OPCODE_TXF_CMS_W:
case SHADER_OPCODE_TXF_UMS:
case SHADER_OPCODE_TXF_MCS:
@ -1083,7 +1079,6 @@ fs_inst::has_sampler_residency() const
case SHADER_OPCODE_TXF_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
case SHADER_OPCODE_TXF_CMS_LOGICAL:
case SHADER_OPCODE_TXS_LOGICAL:
case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
case SHADER_OPCODE_TG4_LOGICAL:
@ -2380,10 +2375,6 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op)
return "txb";
case FS_OPCODE_TXB_LOGICAL:
return "txb_logical";
case SHADER_OPCODE_TXF_CMS:
return "txf_cms";
case SHADER_OPCODE_TXF_CMS_LOGICAL:
return "txf_cms_logical";
case SHADER_OPCODE_TXF_CMS_W:
return "txf_cms_w";
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:

1
src/intel/compiler/brw_fs_copy_propagation.cpp
View file

@ -1168,7 +1168,6 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
case SHADER_OPCODE_TXL_LOGICAL:
case SHADER_OPCODE_TXS_LOGICAL:
case FS_OPCODE_TXB_LOGICAL:
case SHADER_OPCODE_TXF_CMS_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
case SHADER_OPCODE_TXF_UMS_LOGICAL:

1
src/intel/compiler/brw_fs_cse.cpp
View file

@ -88,7 +88,6 @@ is_expression(const fs_visitor *v, const fs_inst *const inst)
case SHADER_OPCODE_TXL_LOGICAL:
case SHADER_OPCODE_TXS_LOGICAL:
case FS_OPCODE_TXB_LOGICAL:
case SHADER_OPCODE_TXF_CMS_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
case SHADER_OPCODE_TXF_UMS_LOGICAL:
case SHADER_OPCODE_TXF_MCS_LOGICAL:

1
src/intel/compiler/brw_fs_lower_simd_width.cpp
View file

@ -323,7 +323,6 @@ brw_fs_get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst)
return MIN2(16, inst->exec_size);
case SHADER_OPCODE_TEX_LOGICAL:
case SHADER_OPCODE_TXF_CMS_LOGICAL:
case SHADER_OPCODE_TXF_UMS_LOGICAL:
case SHADER_OPCODE_TXF_MCS_LOGICAL:
case SHADER_OPCODE_LOD_LOGICAL:

1
src/intel/compiler/brw_ir_performance.cpp
View file

@ -557,7 +557,6 @@ namespace {
case SHADER_OPCODE_TXF_LZ:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXL_LZ:
case SHADER_OPCODE_TXF_CMS:
case SHADER_OPCODE_TXF_CMS_W:
case SHADER_OPCODE_TXF_UMS:
case SHADER_OPCODE_TXF_MCS:

16
src/intel/compiler/brw_lower_logical_sends.cpp
View file

@ -609,9 +609,6 @@ sampler_msg_type(const intel_device_info *devinfo,
case SHADER_OPCODE_TXF_CMS_W:
assert(!has_min_lod);
return GFX9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
case SHADER_OPCODE_TXF_CMS:
assert(!has_min_lod);
return GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
case SHADER_OPCODE_TXF_UMS:
assert(!has_min_lod);
return GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
@ -963,18 +960,16 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op,
coordinate_done = true;
break;
case SHADER_OPCODE_TXF_CMS:
case SHADER_OPCODE_TXF_CMS_W:
case SHADER_OPCODE_TXF_UMS:
case SHADER_OPCODE_TXF_MCS:
if (op == SHADER_OPCODE_TXF_UMS ||
op == SHADER_OPCODE_TXF_CMS ||
op == SHADER_OPCODE_TXF_CMS_W) {
bld.MOV(retype(sources[length++], payload_unsigned_type), sample_index);
}
/* Data from the multisample control surface. */
if (op == SHADER_OPCODE_TXF_CMS || op == SHADER_OPCODE_TXF_CMS_W) {
if (op == SHADER_OPCODE_TXF_CMS_W) {
unsigned num_mcs_components = 1;
/* From the Gfx12HP BSpec: Render Engine - 3D and GPGPU Programs -
@ -1237,9 +1232,7 @@ get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo,
* which is already in 16-bits unlike the other parameters that need forced
* conversion.
*/
if (devinfo->verx10 < 125 ||
(op != SHADER_OPCODE_TXF_CMS_W &&
op != SHADER_OPCODE_TXF_CMS)) {
if (devinfo->verx10 < 125 || op != SHADER_OPCODE_TXF_CMS_W) {
for (unsigned i = 0; i < TEX_LOGICAL_NUM_SRCS; i++) {
assert(src[i].file == BAD_FILE ||
brw_reg_type_to_size(src[i].type) == src_type_size);
@ -1260,7 +1253,6 @@ get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo,
*/
if (op == SHADER_OPCODE_TXF_CMS_W ||
op == SHADER_OPCODE_TXF_CMS ||
op == SHADER_OPCODE_TXF_UMS ||
op == SHADER_OPCODE_TXF_MCS ||
(op == FS_OPCODE_TXB && !inst->has_packed_lod_ai_src &&
@ -2799,10 +2791,6 @@ brw_fs_lower_logical_sends(fs_visitor &s)
lower_sampler_logical_send(ibld, inst, FS_OPCODE_TXB);
break;
case SHADER_OPCODE_TXF_CMS_LOGICAL:
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_CMS);
break;
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXF_CMS_W);