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ac,radv,radeonsi: add ac_tracked_regs

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38740>
This commit is contained in:
Samuel Pitoiset 2025-12-04 14:16:09 +01:00 • committed by Marge Bot
parent c97bd17d4d
commit 44314e1ea6
6 changed files with 21 additions and 25 deletions
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10
src/amd/common/ac_cmdbuf.h
View file

@ -11,6 +11,8 @@
#include "ac_pm4.h" #include "ac_pm4.h"
#include "util/bitset.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
@ -251,6 +253,14 @@ enum ac_tracked_reg
AC_NUM_ALL_TRACKED_REGS, AC_NUM_ALL_TRACKED_REGS,
}; };
struct ac_tracked_regs {
BITSET_DECLARE(reg_saved_mask, AC_NUM_ALL_TRACKED_REGS);
uint32_t reg_value[AC_NUM_ALL_TRACKED_REGS];
uint32_t spi_ps_input_cntl[32];
uint32_t cb_blend_control[8];
uint32_t sx_mrt_blend_opt[8];
};
#define ac_cmdbuf_begin(cs) struct ac_cmdbuf *__cs = (cs); \ #define ac_cmdbuf_begin(cs) struct ac_cmdbuf *__cs = (cs); \
uint32_t __cs_num = __cs->cdw; \ uint32_t __cs_num = __cs->cdw; \
UNUSED uint32_t __cs_num_initial = __cs_num; \ UNUSED uint32_t __cs_num_initial = __cs_num; \

10
src/amd/vulkan/radv_cmd_buffer.h
View file

@ -279,14 +279,6 @@ enum rgp_flush_bits {
RGP_FLUSH_INVAL_L1 = 0x8000, RGP_FLUSH_INVAL_L1 = 0x8000,
}; };
struct radv_tracked_regs {
BITSET_DECLARE(reg_saved_mask, AC_NUM_ALL_TRACKED_REGS);
uint32_t reg_value[AC_NUM_ALL_TRACKED_REGS];
uint32_t spi_ps_input_cntl[32];
uint32_t cb_blend_control[MAX_RTS];
uint32_t sx_mrt_blend_opt[MAX_RTS];
};
enum radv_depth_clamp_mode { enum radv_depth_clamp_mode {
RADV_DEPTH_CLAMP_MODE_VIEWPORT = 0, /* Clamp to the viewport min/max depth bounds */ RADV_DEPTH_CLAMP_MODE_VIEWPORT = 0, /* Clamp to the viewport min/max depth bounds */
RADV_DEPTH_CLAMP_MODE_USER_DEFINED = 1, /* Range set using VK_EXT_depth_clamp_control */ RADV_DEPTH_CLAMP_MODE_USER_DEFINED = 1, /* Range set using VK_EXT_depth_clamp_control */
@ -477,7 +469,7 @@ struct radv_cmd_stream {
bool context_roll_without_scissor_emitted; bool context_roll_without_scissor_emitted;
struct radv_tracked_regs tracked_regs; struct ac_tracked_regs tracked_regs;
enum amd_ip_type hw_ip; enum amd_ip_type hw_ip;
struct ac_buffered_sh_regs buffered_sh_regs; struct ac_buffered_sh_regs buffered_sh_regs;

2
src/amd/vulkan/radv_cs.c
View file

@ -448,7 +448,7 @@ radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, e
static void static void
radv_init_tracked_regs(struct radv_cmd_stream *cs) radv_init_tracked_regs(struct radv_cmd_stream *cs)
{ {
struct radv_tracked_regs *tracked_regs = &cs->tracked_regs; struct ac_tracked_regs *tracked_regs = &cs->tracked_regs;
/* Mark all registers as unknown. */ /* Mark all registers as unknown. */
memset(tracked_regs->reg_value, 0, AC_NUM_ALL_TRACKED_REGS * sizeof(uint32_t)); memset(tracked_regs->reg_value, 0, AC_NUM_ALL_TRACKED_REGS * sizeof(uint32_t));

16
src/amd/vulkan/radv_cs.h
View file

@ -76,7 +76,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need
#define radeon_opt_set_context_reg(reg, reg_enum, value) \ #define radeon_opt_set_context_reg(reg, reg_enum, value) \
do { \ do { \
struct radv_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \
const uint32_t __value = (value); \ const uint32_t __value = (value); \
if (!BITSET_TEST(__tracked_regs->reg_saved_mask, (reg_enum)) || \ if (!BITSET_TEST(__tracked_regs->reg_saved_mask, (reg_enum)) || \
__tracked_regs->reg_value[(reg_enum)] != __value) { \ __tracked_regs->reg_value[(reg_enum)] != __value) { \
@ -89,7 +89,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need
#define radeon_opt_set_context_reg2(reg, reg_enum, v1, v2) \ #define radeon_opt_set_context_reg2(reg, reg_enum, v1, v2) \
do { \ do { \
struct radv_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \
const uint32_t __v1 = (v1), __v2 = (v2); \ const uint32_t __v1 = (v1), __v2 = (v2); \
if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1, 0x3) || \ if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1, 0x3) || \
__tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2) { \ __tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2) { \
@ -105,7 +105,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need
#define radeon_opt_set_context_reg3(reg, reg_enum, v1, v2, v3) \ #define radeon_opt_set_context_reg3(reg, reg_enum, v1, v2, v3) \
do { \ do { \
struct radv_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \
const uint32_t __v1 = (v1), __v2 = (v2), __v3 = (v3); \ const uint32_t __v1 = (v1), __v2 = (v2), __v3 = (v3); \
if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 2, 0x7) || \ if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 2, 0x7) || \
__tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2 || \ __tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2 || \
@ -124,7 +124,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need
#define radeon_opt_set_context_reg4(reg, reg_enum, v1, v2, v3, v4) \ #define radeon_opt_set_context_reg4(reg, reg_enum, v1, v2, v3, v4) \
do { \ do { \
struct radv_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \
const uint32_t __v1 = (v1), __v2 = (v2), __v3 = (v3), __v4 = (v4); \ const uint32_t __v1 = (v1), __v2 = (v2), __v3 = (v3), __v4 = (v4); \
if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 3, 0xf) || \ if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 3, 0xf) || \
__tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2 || \ __tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2 || \
@ -211,7 +211,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need
/* Set 1 context register optimally. */ /* Set 1 context register optimally. */
#define __gfx12_opt_set_reg(reg, reg_enum, value, base_offset) \ #define __gfx12_opt_set_reg(reg, reg_enum, value, base_offset) \
do { \ do { \
struct radv_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \
const uint32_t __value = (value); \ const uint32_t __value = (value); \
if (!BITSET_TEST(__tracked_regs->reg_saved_mask, (reg_enum)) || \ if (!BITSET_TEST(__tracked_regs->reg_saved_mask, (reg_enum)) || \
__tracked_regs->reg_value[(reg_enum)] != __value) { \ __tracked_regs->reg_value[(reg_enum)] != __value) { \
@ -224,7 +224,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need
/* Set 2 context registers optimally. */ /* Set 2 context registers optimally. */
#define __gfx12_opt_set_reg2(reg, reg_enum, v1, v2, base_offset) \ #define __gfx12_opt_set_reg2(reg, reg_enum, v1, v2, base_offset) \
do { \ do { \
struct radv_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \
const uint32_t __v1 = (v1), __v2 = (v2); \ const uint32_t __v1 = (v1), __v2 = (v2); \
if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1, 0x3) || \ if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1, 0x3) || \
__tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2) { \ __tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2) { \
@ -263,7 +263,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need
#define gfx11_opt_push_reg(reg, reg_enum, value, prefix_name, buffer, reg_count) \ #define gfx11_opt_push_reg(reg, reg_enum, value, prefix_name, buffer, reg_count) \
do { \ do { \
struct radv_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \
const uint32_t __value = (value); \ const uint32_t __value = (value); \
if (!BITSET_TEST(__tracked_regs->reg_saved_mask, (reg_enum)) || \ if (!BITSET_TEST(__tracked_regs->reg_saved_mask, (reg_enum)) || \
__tracked_regs->reg_value[(reg_enum)] != __value) { \ __tracked_regs->reg_value[(reg_enum)] != __value) { \
@ -275,7 +275,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need
#define gfx11_opt_push_reg2(reg, reg_enum, v1, v2, prefix_name, buffer, reg_count) \ #define gfx11_opt_push_reg2(reg, reg_enum, v1, v2, prefix_name, buffer, reg_count) \
do { \ do { \
struct radv_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \
const uint32_t __v1 = (v1), __v2 = (v2); \ const uint32_t __v1 = (v1), __v2 = (v2); \
if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1, 0x3) || \ if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1, 0x3) || \
__tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2) { \ __tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2) { \

2
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -1324,7 +1324,7 @@ struct si_context {
bool with_db; bool with_db;
} force_shader_coherency; } force_shader_coherency;
struct si_tracked_regs tracked_regs; struct ac_tracked_regs tracked_regs;
/* Resources that need to be flushed, but will not get an explicit /* Resources that need to be flushed, but will not get an explicit
* flush_resource from the frontend and that will need to get flushed during * flush_resource from the frontend and that will need to get flushed during

6
src/gallium/drivers/radeonsi/si_state.h
View file

@ -273,12 +273,6 @@ struct si_shader_data {
#define BASEVERTEX_DRAWID_MASK (BASEVERTEX_MASK | DRAWID_MASK) #define BASEVERTEX_DRAWID_MASK (BASEVERTEX_MASK | DRAWID_MASK)
#define BASEVERTEX_DRAWID_STARTINSTANCE_MASK (BASEVERTEX_MASK | DRAWID_MASK | STARTINSTANCE_MASK) #define BASEVERTEX_DRAWID_STARTINSTANCE_MASK (BASEVERTEX_MASK | DRAWID_MASK | STARTINSTANCE_MASK)
struct si_tracked_regs {
BITSET_DECLARE(reg_saved_mask, AC_NUM_ALL_TRACKED_REGS);
uint32_t reg_value[AC_NUM_ALL_TRACKED_REGS];
uint32_t spi_ps_input_cntl[32];
};
/* Private read-write buffer slots. */ /* Private read-write buffer slots. */
enum enum
{ {