diff --git a/src/amd/common/ac_cmdbuf.h b/src/amd/common/ac_cmdbuf.h index 613ee25bbc5..d63f64ba648 100644 --- a/src/amd/common/ac_cmdbuf.h +++ b/src/amd/common/ac_cmdbuf.h @@ -11,6 +11,8 @@ #include "ac_pm4.h" +#include "util/bitset.h" + #ifdef __cplusplus extern "C" { #endif @@ -251,6 +253,14 @@ enum ac_tracked_reg AC_NUM_ALL_TRACKED_REGS, }; +struct ac_tracked_regs { + BITSET_DECLARE(reg_saved_mask, AC_NUM_ALL_TRACKED_REGS); + uint32_t reg_value[AC_NUM_ALL_TRACKED_REGS]; + uint32_t spi_ps_input_cntl[32]; + uint32_t cb_blend_control[8]; + uint32_t sx_mrt_blend_opt[8]; +}; + #define ac_cmdbuf_begin(cs) struct ac_cmdbuf *__cs = (cs); \ uint32_t __cs_num = __cs->cdw; \ UNUSED uint32_t __cs_num_initial = __cs_num; \ diff --git a/src/amd/vulkan/radv_cmd_buffer.h b/src/amd/vulkan/radv_cmd_buffer.h index eb7c2681b3a..6a937c6dac2 100644 --- a/src/amd/vulkan/radv_cmd_buffer.h +++ b/src/amd/vulkan/radv_cmd_buffer.h @@ -279,14 +279,6 @@ enum rgp_flush_bits { RGP_FLUSH_INVAL_L1 = 0x8000, }; -struct radv_tracked_regs { - BITSET_DECLARE(reg_saved_mask, AC_NUM_ALL_TRACKED_REGS); - uint32_t reg_value[AC_NUM_ALL_TRACKED_REGS]; - uint32_t spi_ps_input_cntl[32]; - uint32_t cb_blend_control[MAX_RTS]; - uint32_t sx_mrt_blend_opt[MAX_RTS]; -}; - enum radv_depth_clamp_mode { RADV_DEPTH_CLAMP_MODE_VIEWPORT = 0, /* Clamp to the viewport min/max depth bounds */ RADV_DEPTH_CLAMP_MODE_USER_DEFINED = 1, /* Range set using VK_EXT_depth_clamp_control */ @@ -477,7 +469,7 @@ struct radv_cmd_stream { bool context_roll_without_scissor_emitted; - struct radv_tracked_regs tracked_regs; + struct ac_tracked_regs tracked_regs; enum amd_ip_type hw_ip; struct ac_buffered_sh_regs buffered_sh_regs; diff --git a/src/amd/vulkan/radv_cs.c b/src/amd/vulkan/radv_cs.c index 5f3a64605e4..8abcd96e1f0 100644 --- a/src/amd/vulkan/radv_cs.c +++ b/src/amd/vulkan/radv_cs.c @@ -448,7 +448,7 @@ radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, e static void radv_init_tracked_regs(struct radv_cmd_stream *cs) { - struct radv_tracked_regs *tracked_regs = &cs->tracked_regs; + struct ac_tracked_regs *tracked_regs = &cs->tracked_regs; /* Mark all registers as unknown. */ memset(tracked_regs->reg_value, 0, AC_NUM_ALL_TRACKED_REGS * sizeof(uint32_t)); diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h index dea6d464654..c749e4e98b3 100644 --- a/src/amd/vulkan/radv_cs.h +++ b/src/amd/vulkan/radv_cs.h @@ -76,7 +76,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need #define radeon_opt_set_context_reg(reg, reg_enum, value) \ do { \ - struct radv_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ + struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ const uint32_t __value = (value); \ if (!BITSET_TEST(__tracked_regs->reg_saved_mask, (reg_enum)) || \ __tracked_regs->reg_value[(reg_enum)] != __value) { \ @@ -89,7 +89,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need #define radeon_opt_set_context_reg2(reg, reg_enum, v1, v2) \ do { \ - struct radv_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ + struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ const uint32_t __v1 = (v1), __v2 = (v2); \ if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1, 0x3) || \ __tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2) { \ @@ -105,7 +105,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need #define radeon_opt_set_context_reg3(reg, reg_enum, v1, v2, v3) \ do { \ - struct radv_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ + struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ const uint32_t __v1 = (v1), __v2 = (v2), __v3 = (v3); \ if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 2, 0x7) || \ __tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2 || \ @@ -124,7 +124,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need #define radeon_opt_set_context_reg4(reg, reg_enum, v1, v2, v3, v4) \ do { \ - struct radv_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ + struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ const uint32_t __v1 = (v1), __v2 = (v2), __v3 = (v3), __v4 = (v4); \ if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 3, 0xf) || \ __tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2 || \ @@ -211,7 +211,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need /* Set 1 context register optimally. */ #define __gfx12_opt_set_reg(reg, reg_enum, value, base_offset) \ do { \ - struct radv_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ + struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ const uint32_t __value = (value); \ if (!BITSET_TEST(__tracked_regs->reg_saved_mask, (reg_enum)) || \ __tracked_regs->reg_value[(reg_enum)] != __value) { \ @@ -224,7 +224,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need /* Set 2 context registers optimally. */ #define __gfx12_opt_set_reg2(reg, reg_enum, v1, v2, base_offset) \ do { \ - struct radv_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ + struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ const uint32_t __v1 = (v1), __v2 = (v2); \ if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1, 0x3) || \ __tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2) { \ @@ -263,7 +263,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need #define gfx11_opt_push_reg(reg, reg_enum, value, prefix_name, buffer, reg_count) \ do { \ - struct radv_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ + struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ const uint32_t __value = (value); \ if (!BITSET_TEST(__tracked_regs->reg_saved_mask, (reg_enum)) || \ __tracked_regs->reg_value[(reg_enum)] != __value) { \ @@ -275,7 +275,7 @@ radeon_check_space(struct radeon_winsys *ws, struct ac_cmdbuf *cs, unsigned need #define gfx11_opt_push_reg2(reg, reg_enum, v1, v2, prefix_name, buffer, reg_count) \ do { \ - struct radv_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ + struct ac_tracked_regs *__tracked_regs = &__rcs->tracked_regs; \ const uint32_t __v1 = (v1), __v2 = (v2); \ if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1, 0x3) || \ __tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2) { \ diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 43f726b89f2..a1306ba3a76 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -1324,7 +1324,7 @@ struct si_context { bool with_db; } force_shader_coherency; - struct si_tracked_regs tracked_regs; + struct ac_tracked_regs tracked_regs; /* Resources that need to be flushed, but will not get an explicit * flush_resource from the frontend and that will need to get flushed during diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index e5e9559ead3..95a12680896 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -273,12 +273,6 @@ struct si_shader_data { #define BASEVERTEX_DRAWID_MASK (BASEVERTEX_MASK | DRAWID_MASK) #define BASEVERTEX_DRAWID_STARTINSTANCE_MASK (BASEVERTEX_MASK | DRAWID_MASK | STARTINSTANCE_MASK) -struct si_tracked_regs { - BITSET_DECLARE(reg_saved_mask, AC_NUM_ALL_TRACKED_REGS); - uint32_t reg_value[AC_NUM_ALL_TRACKED_REGS]; - uint32_t spi_ps_input_cntl[32]; -}; - /* Private read-write buffer slots. */ enum {