panfrost,panvk: Move lower_texture_early inside preproc

Signed-off-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40844>
This commit is contained in:
Lorenzo Rossi 2026-04-06 13:57:51 +02:00 committed by Marge Bot
parent e24228e327
commit 43ba475d4c
7 changed files with 14 additions and 24 deletions

View file

@ -541,7 +541,6 @@ pan_preload_get_shader(struct pan_fb_preload_cache *cache,
BITSET_SET(b.shader->info.textures_used, i);
pan_preprocess_nir(b.shader, inputs.gpu_id);
pan_nir_lower_texture_early(b.shader, inputs.gpu_id);
pan_postprocess_nir(b.shader, inputs.gpu_id);
if (PAN_ARCH == 4) {

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@ -111,7 +111,6 @@ panfrost_shader_compile(struct panfrost_screen *screen, const nir_shader *ir,
*/
if (mesa_shader_stage_is_compute(s->info.stage)) {
pan_preprocess_nir(s, panfrost_device_gpu_id(dev));
pan_nir_lower_texture_early(s, panfrost_device_gpu_id(dev));
}
struct pan_compile_inputs inputs = {
@ -539,7 +538,6 @@ panfrost_create_shader_state(struct pipe_context *pctx,
/* Then run the suite of lowering and optimization, including I/O lowering */
struct panfrost_device *dev = pan_device(pctx->screen);
pan_preprocess_nir(nir, panfrost_device_gpu_id(dev));
pan_nir_lower_texture_early(nir, panfrost_device_gpu_id(dev));
NIR_PASS(_, nir, nir_lower_indirect_derefs_to_if_else_trees,
nir_var_shader_in | nir_var_shader_out, UINT32_MAX);

View file

@ -420,7 +420,6 @@ main(int argc, const char **argv)
glsl_get_cl_type_size_align);
pan_preprocess_nir(s, inputs.gpu_id);
pan_nir_lower_texture_early(s, inputs.gpu_id);
NIR_PASS(_, s, nir_opt_deref);
NIR_PASS(_, s, nir_lower_vars_to_ssa);

View file

@ -67,6 +67,20 @@ pan_preprocess_nir(nir_shader *nir, uint64_t gpu_id)
bifrost_preprocess_nir(nir, gpu_id);
else
midgard_preprocess_nir(nir, gpu_id);
/* Lower textures early */
nir_lower_tex_options lower_tex_options = {
.lower_txs_lod = true,
.lower_txp = ~0,
.lower_tg4_offsets = true,
.lower_tg4_broadcom_swizzle = true,
.lower_txd = pan_arch(gpu_id) < 6,
.lower_txd_cube_map = true,
.lower_invalid_implicit_lod = true,
.lower_index_to_offset = pan_arch(gpu_id) >= 6,
};
NIR_PASS(_, nir, nir_lower_tex, &lower_tex_options);
}
void
@ -85,22 +99,6 @@ pan_postprocess_nir(nir_shader *nir, uint64_t gpu_id)
midgard_postprocess_nir(nir, gpu_id);
}
void
pan_nir_lower_texture_early(nir_shader *nir, uint64_t gpu_id)
{
nir_lower_tex_options lower_tex_options = {
.lower_txs_lod = true,
.lower_txp = ~0,
.lower_tg4_offsets = true,
.lower_tg4_broadcom_swizzle = true,
.lower_txd = pan_arch(gpu_id) < 6,
.lower_txd_cube_map = true,
.lower_invalid_implicit_lod = true,
.lower_index_to_offset = pan_arch(gpu_id) >= 6,
};
NIR_PASS(_, nir, nir_lower_tex, &lower_tex_options);
}
/** Converts a per-component mask to a byte mask */
uint16_t
pan_to_bytemask(unsigned bytes, unsigned mask)

View file

@ -72,8 +72,6 @@ bool pan_nir_lower_image_index(nir_shader *shader,
bool pan_nir_lower_texel_buffer_fetch_index(nir_shader *shader,
unsigned attrib_offset);
void pan_nir_lower_texture_early(nir_shader *nir, uint64_t gpu_id);
nir_alu_type
pan_unpacked_type_for_format(const struct util_format_description *desc);

View file

@ -221,7 +221,6 @@ get_frame_shader(struct panvk_device *dev,
};
pan_preprocess_nir(nir, inputs.gpu_id);
pan_nir_lower_texture_early(nir, inputs.gpu_id);
pan_postprocess_nir(nir, inputs.gpu_id);
VkResult result = panvk_per_arch(create_internal_shader)(

View file

@ -486,7 +486,6 @@ panvk_preprocess_nir(struct vk_physical_device *vk_pdev,
*
* This would give us a better place to do panvk-specific lowering.
*/
pan_nir_lower_texture_early(nir, pdev->kmod.dev->props.gpu_id);
NIR_PASS(_, nir, nir_lower_system_values);
nir_lower_compute_system_values_options options = {