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panfrost,panvk: Move lower_texture_late inside postproc
Signed-off-by: Lorenzo Rossi <lorenzo.rossi@collabora.com> Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com> Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40844>
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8 changed files with 15 additions and 24 deletions
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@ -188,7 +188,6 @@ panfrost_shader_compile(struct panfrost_screen *screen, const nir_shader *ir,
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NIR_PASS(_, s, panfrost_nir_lower_res_indices, &inputs);
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pan_postprocess_nir(s, panfrost_device_gpu_id(dev));
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pan_nir_lower_texture_late(s, inputs.gpu_id);
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if (s->info.stage == MESA_SHADER_VERTEX) {
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NIR_PASS(_, s, nir_inline_sysval,
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@ -430,7 +430,6 @@ main(int argc, const char **argv)
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nir_address_format_62bit_generic);
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pan_postprocess_nir(s, inputs.gpu_id);
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pan_nir_lower_texture_late(s, inputs.gpu_id);
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NIR_PASS(_, s, nir_shader_intrinsics_pass, lower_sysvals,
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nir_metadata_control_flow, NULL);
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@ -65,8 +65,6 @@ bifrost_precompiled_kernel_prepare_push_uniforms(
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void bifrost_preprocess_nir(nir_shader *nir, uint64_t gpu_id);
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void bifrost_optimize_nir(nir_shader *nir, uint64_t gpu_id);
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void bifrost_postprocess_nir(nir_shader *nir, uint64_t gpu_id);
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void bifrost_lower_texture_nir(nir_shader *nir, uint64_t gpu_id);
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void bifrost_lower_texture_late_nir(nir_shader *nir, uint64_t gpu_id);
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void bifrost_compile_shader_nir(nir_shader *nir,
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const struct pan_compile_inputs *inputs,
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@ -714,6 +714,9 @@ mem_access_size_align_cb(nir_intrinsic_op intrin, uint8_t bytes,
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};
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}
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static void bi_lower_texture_nir(nir_shader *nir, uint64_t gpu_id);
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static void bi_lower_texture_late_nir(nir_shader *nir, uint64_t gpu_id);
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void
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bifrost_postprocess_nir(nir_shader *nir, uint64_t gpu_id)
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{
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@ -727,7 +730,7 @@ bifrost_postprocess_nir(nir_shader *nir, uint64_t gpu_id)
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NIR_PASS(_, nir, nir_opt_sink, move_all);
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NIR_PASS(_, nir, nir_opt_move, move_all);
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bifrost_lower_texture_nir(nir, gpu_id);
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bi_lower_texture_nir(nir, gpu_id);
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if (nir->info.stage == MESA_SHADER_FRAGMENT) {
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NIR_PASS(_, nir, pan_nir_lower_noperspective_fs);
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@ -816,10 +819,12 @@ bifrost_postprocess_nir(nir_shader *nir, uint64_t gpu_id)
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NIR_PASS(_, nir, nir_lower_alu);
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NIR_PASS(_, nir, nir_lower_frag_coord_to_pixel_coord);
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NIR_PASS(_, nir, pan_nir_lower_var_special_pan);
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bi_lower_texture_late_nir(nir, gpu_id);
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}
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void
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bifrost_lower_texture_nir(nir_shader *nir, uint64_t gpu_id)
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static void
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bi_lower_texture_nir(nir_shader *nir, uint64_t gpu_id)
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{
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NIR_PASS(_, nir, nir_lower_image_atomics_to_global, NULL, NULL);
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@ -964,8 +969,13 @@ pan_nir_lower_buf_image_access(nir_shader *shader, unsigned arch)
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nir_metadata_control_flow, &arch);
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}
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void
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bifrost_lower_texture_late_nir(nir_shader *nir, uint64_t gpu_id)
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/* This must be called after any lowering of resource indices
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* (panfrost_nir_lower_res_indices / panvk_per_arch(nir_lower_descriptors))
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* and lowering of attribute indices (pan_nir_lower_image_index /
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* pan_nir_lower_texel_buffer_fetch_index)
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*/
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static void
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bi_lower_texture_late_nir(nir_shader *nir, uint64_t gpu_id)
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{
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NIR_PASS(_, nir, pan_nir_lower_texel_buffer_fetch, pan_arch(gpu_id));
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NIR_PASS(_, nir, pan_nir_lower_buf_image_access, pan_arch(gpu_id));
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@ -101,18 +101,6 @@ pan_nir_lower_texture_early(nir_shader *nir, uint64_t gpu_id)
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NIR_PASS(_, nir, nir_lower_tex, &lower_tex_options);
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}
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void
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pan_nir_lower_texture_late(nir_shader *nir, uint64_t gpu_id)
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{
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/* This must be called after any lowering of resource indices
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* (panfrost_nir_lower_res_indices / panvk_per_arch(nir_lower_descriptors))
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* and lowering of attribute indices (pan_nir_lower_image_index /
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* pan_nir_lower_texel_buffer_fetch_index) */
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if (pan_arch(gpu_id) >= 6)
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bifrost_lower_texture_late_nir(nir, gpu_id);
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}
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/** Converts a per-component mask to a byte mask */
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uint16_t
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pan_to_bytemask(unsigned bytes, unsigned mask)
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@ -73,7 +73,6 @@ bool pan_nir_lower_texel_buffer_fetch_index(nir_shader *shader,
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unsigned attrib_offset);
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void pan_nir_lower_texture_early(nir_shader *nir, uint64_t gpu_id);
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void pan_nir_lower_texture_late(nir_shader *nir, uint64_t gpu_id);
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nir_alu_type
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pan_unpacked_type_for_format(const struct util_format_description *desc);
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@ -223,7 +223,6 @@ get_frame_shader(struct panvk_device *dev,
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pan_preprocess_nir(nir, inputs.gpu_id);
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pan_nir_lower_texture_early(nir, inputs.gpu_id);
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pan_postprocess_nir(nir, inputs.gpu_id);
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pan_nir_lower_texture_late(nir, inputs.gpu_id);
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VkResult result = panvk_per_arch(create_internal_shader)(
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dev, nir, &inputs, &shader);
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@ -981,7 +981,6 @@ panvk_compile_nir(struct panvk_device *dev, nir_shader *nir,
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}
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pan_postprocess_nir(nir, input.gpu_id);
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pan_nir_lower_texture_late(nir, input.gpu_id);
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if (noperspective_varyings && nir->info.stage == MESA_SHADER_VERTEX) {
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NIR_PASS(_, nir, nir_inline_sysval,
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