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nir: add pixel_coord_intel

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This is a 2x16 bitpacked version of load_pixel_coord which maps directly to the
hardware value and is much easier for Jay to consume due to the sadness that is
true 16-bit on Intel. Jay will lower to this internally.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40835>
This commit is contained in:
Alyssa Rosenzweig 2026-02-24 11:53:23 -05:00 • committed by Marge Bot
parent bd6d210386
commit 4356ad1bf5
2 changed files with 4 additions and 0 deletions
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1
src/compiler/nir/nir_divergence_analysis.c
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@ -873,6 +873,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
case nir_intrinsic_load_frag_coord_unscaled_ir3:
case nir_intrinsic_load_frag_coord_gmem_ir3:
case nir_intrinsic_load_pixel_coord:
case nir_intrinsic_load_pixel_coord_intel:
case nir_intrinsic_load_fully_covered:
case nir_intrinsic_load_sample_pos:
case nir_intrinsic_load_sample_pos_or_center:

3
src/compiler/nir/nir_intrinsics.py
View file

@ -2597,6 +2597,9 @@ system_value("fs_start_intel", 2, bit_sizes=[32])
system_value("fs_z_c_intel", 2, bit_sizes=[32])
system_value("fs_z_c0_intel", 1, bit_sizes=[32])
# Lower 16-bit has pixel X coord, upper 16-bit has pixel Y coord
system_value("pixel_coord_intel", 1, bit_sizes=[32])
# Read the attribute thread payload at a given byte offset
# src[] = { offset }
load("attribute_payload_intel", [1], flags=[CAN_ELIMINATE, CAN_REORDER])