From 4356ad1bf56e510f696974c9a35d8149357b3664 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Tue, 24 Feb 2026 11:53:23 -0500 Subject: [PATCH] nir: add pixel_coord_intel This is a 2x16 bitpacked version of load_pixel_coord which maps directly to the hardware value and is much easier for Jay to consume due to the sadness that is true 16-bit on Intel. Jay will lower to this internally. Signed-off-by: Alyssa Rosenzweig Reviewed-by: Lionel Landwerlin Reviewed-by: Kenneth Graunke Part-of: --- src/compiler/nir/nir_divergence_analysis.c | 1 + src/compiler/nir/nir_intrinsics.py | 3 +++ 2 files changed, 4 insertions(+) diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index 63fd6a1ba66..9d8ea263c6b 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -873,6 +873,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state) case nir_intrinsic_load_frag_coord_unscaled_ir3: case nir_intrinsic_load_frag_coord_gmem_ir3: case nir_intrinsic_load_pixel_coord: + case nir_intrinsic_load_pixel_coord_intel: case nir_intrinsic_load_fully_covered: case nir_intrinsic_load_sample_pos: case nir_intrinsic_load_sample_pos_or_center: diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 395e285ae47..2c6612bef99 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -2597,6 +2597,9 @@ system_value("fs_start_intel", 2, bit_sizes=[32]) system_value("fs_z_c_intel", 2, bit_sizes=[32]) system_value("fs_z_c0_intel", 1, bit_sizes=[32]) +# Lower 16-bit has pixel X coord, upper 16-bit has pixel Y coord +system_value("pixel_coord_intel", 1, bit_sizes=[32]) + # Read the attribute thread payload at a given byte offset # src[] = { offset } load("attribute_payload_intel", [1], flags=[CAN_ELIMINATE, CAN_REORDER])