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freedreno: FD_SHADER_DEBUG -> IR3_SHADER_DEBUG
Only used by ir3, so move it into ir3 to be more self contained. Signed-off-by: Rob Clark <robdclark@gmail.com>
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8a654f092e
commit
424d75656f
4 changed files with 34 additions and 33 deletions
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@ -30,27 +30,6 @@
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#include "compiler/shader_enums.h"
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#include "util/u_debug.h"
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enum fd_shader_debug {
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FD_DBG_SHADER_VS = 0x01,
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FD_DBG_SHADER_FS = 0x02,
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FD_DBG_SHADER_CS = 0x04,
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};
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extern enum fd_shader_debug fd_shader_debug;
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static inline bool
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shader_debug_enabled(gl_shader_stage type)
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{
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switch (type) {
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case MESA_SHADER_VERTEX: return !!(fd_shader_debug & FD_DBG_SHADER_VS);
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case MESA_SHADER_FRAGMENT: return !!(fd_shader_debug & FD_DBG_SHADER_FS);
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case MESA_SHADER_COMPUTE: return !!(fd_shader_debug & FD_DBG_SHADER_CS);
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default:
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debug_assert(0);
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return false;
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}
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}
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/* bitmask of debug flags */
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enum debug_t {
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PRINT_RAW = 0x1, /* dump raw hexdump */
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@ -96,17 +96,6 @@ int fd_mesa_debug = 0;
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bool fd_binning_enabled = true;
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static bool glsl120 = false;
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static const struct debug_named_value shader_debug_options[] = {
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{"vs", FD_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
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{"fs", FD_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
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{"cs", FD_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
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DEBUG_NAMED_VALUE_END
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};
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DEBUG_GET_ONCE_FLAGS_OPTION(fd_shader_debug, "FD_SHADER_DEBUG", shader_debug_options, 0)
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enum fd_shader_debug fd_shader_debug = 0;
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static const char *
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fd_screen_get_name(struct pipe_screen *pscreen)
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{
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@ -703,7 +692,6 @@ fd_screen_create(struct fd_device *dev)
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uint64_t val;
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fd_mesa_debug = debug_get_option_fd_mesa_debug();
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fd_shader_debug = debug_get_option_fd_shader_debug();
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if (fd_mesa_debug & FD_DBG_NOBIN)
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fd_binning_enabled = false;
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@ -28,10 +28,23 @@
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#include "ir3_compiler.h"
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static const struct debug_named_value shader_debug_options[] = {
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{"vs", IR3_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
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{"fs", IR3_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
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{"cs", IR3_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
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DEBUG_NAMED_VALUE_END
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};
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DEBUG_GET_ONCE_FLAGS_OPTION(ir3_shader_debug, "IR3_SHADER_DEBUG", shader_debug_options, 0)
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enum ir3_shader_debug ir3_shader_debug = 0;
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struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id)
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{
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struct ir3_compiler *compiler = rzalloc(NULL, struct ir3_compiler);
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ir3_shader_debug = debug_get_option_ir3_shader_debug();
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compiler->dev = dev;
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compiler->gpu_id = gpu_id;
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compiler->set = ir3_ra_alloc_reg_set(compiler);
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@ -70,4 +70,25 @@ struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id
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int ir3_compile_shader_nir(struct ir3_compiler *compiler,
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struct ir3_shader_variant *so);
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enum ir3_shader_debug {
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IR3_DBG_SHADER_VS = 0x01,
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IR3_DBG_SHADER_FS = 0x02,
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IR3_DBG_SHADER_CS = 0x04,
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};
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extern enum ir3_shader_debug ir3_shader_debug;
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static inline bool
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shader_debug_enabled(gl_shader_stage type)
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{
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switch (type) {
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case MESA_SHADER_VERTEX: return !!(ir3_shader_debug & IR3_DBG_SHADER_VS);
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case MESA_SHADER_FRAGMENT: return !!(ir3_shader_debug & IR3_DBG_SHADER_FS);
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case MESA_SHADER_COMPUTE: return !!(ir3_shader_debug & IR3_DBG_SHADER_CS);
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default:
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debug_assert(0);
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return false;
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}
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}
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#endif /* IR3_COMPILER_H_ */
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