freedreno: FD_SHADER_DEBUG -> IR3_SHADER_DEBUG

Only used by ir3, so move it into ir3 to be more self contained.

Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark 2018-11-09 10:57:18 -05:00
parent 8a654f092e
commit 424d75656f
4 changed files with 34 additions and 33 deletions

View file

@ -30,27 +30,6 @@
#include "compiler/shader_enums.h"
#include "util/u_debug.h"
enum fd_shader_debug {
FD_DBG_SHADER_VS = 0x01,
FD_DBG_SHADER_FS = 0x02,
FD_DBG_SHADER_CS = 0x04,
};
extern enum fd_shader_debug fd_shader_debug;
static inline bool
shader_debug_enabled(gl_shader_stage type)
{
switch (type) {
case MESA_SHADER_VERTEX: return !!(fd_shader_debug & FD_DBG_SHADER_VS);
case MESA_SHADER_FRAGMENT: return !!(fd_shader_debug & FD_DBG_SHADER_FS);
case MESA_SHADER_COMPUTE: return !!(fd_shader_debug & FD_DBG_SHADER_CS);
default:
debug_assert(0);
return false;
}
}
/* bitmask of debug flags */
enum debug_t {
PRINT_RAW = 0x1, /* dump raw hexdump */

View file

@ -96,17 +96,6 @@ int fd_mesa_debug = 0;
bool fd_binning_enabled = true;
static bool glsl120 = false;
static const struct debug_named_value shader_debug_options[] = {
{"vs", FD_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
{"fs", FD_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
{"cs", FD_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
DEBUG_NAMED_VALUE_END
};
DEBUG_GET_ONCE_FLAGS_OPTION(fd_shader_debug, "FD_SHADER_DEBUG", shader_debug_options, 0)
enum fd_shader_debug fd_shader_debug = 0;
static const char *
fd_screen_get_name(struct pipe_screen *pscreen)
{
@ -703,7 +692,6 @@ fd_screen_create(struct fd_device *dev)
uint64_t val;
fd_mesa_debug = debug_get_option_fd_mesa_debug();
fd_shader_debug = debug_get_option_fd_shader_debug();
if (fd_mesa_debug & FD_DBG_NOBIN)
fd_binning_enabled = false;

View file

@ -28,10 +28,23 @@
#include "ir3_compiler.h"
static const struct debug_named_value shader_debug_options[] = {
{"vs", IR3_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
{"fs", IR3_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
{"cs", IR3_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
DEBUG_NAMED_VALUE_END
};
DEBUG_GET_ONCE_FLAGS_OPTION(ir3_shader_debug, "IR3_SHADER_DEBUG", shader_debug_options, 0)
enum ir3_shader_debug ir3_shader_debug = 0;
struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id)
{
struct ir3_compiler *compiler = rzalloc(NULL, struct ir3_compiler);
ir3_shader_debug = debug_get_option_ir3_shader_debug();
compiler->dev = dev;
compiler->gpu_id = gpu_id;
compiler->set = ir3_ra_alloc_reg_set(compiler);

View file

@ -70,4 +70,25 @@ struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id
int ir3_compile_shader_nir(struct ir3_compiler *compiler,
struct ir3_shader_variant *so);
enum ir3_shader_debug {
IR3_DBG_SHADER_VS = 0x01,
IR3_DBG_SHADER_FS = 0x02,
IR3_DBG_SHADER_CS = 0x04,
};
extern enum ir3_shader_debug ir3_shader_debug;
static inline bool
shader_debug_enabled(gl_shader_stage type)
{
switch (type) {
case MESA_SHADER_VERTEX: return !!(ir3_shader_debug & IR3_DBG_SHADER_VS);
case MESA_SHADER_FRAGMENT: return !!(ir3_shader_debug & IR3_DBG_SHADER_FS);
case MESA_SHADER_COMPUTE: return !!(ir3_shader_debug & IR3_DBG_SHADER_CS);
default:
debug_assert(0);
return false;
}
}
#endif /* IR3_COMPILER_H_ */