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radv: fix 16-bit support in radv_lower_vs_input

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Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: b366fef091 ("radv: optimize the number of loaded components for VS inputs in NIR")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18225>
(cherry picked from commit 9ae13a9bd3)
This commit is contained in:
Rhys Perry 2022-08-04 17:54:56 +01:00 • committed by Dylan Baker
parent 70dcad3214
commit 3f3ecdccb1
2 changed files with 4 additions and 3 deletions
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2
.pick_status.json
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@ -9886,7 +9886,7 @@
"description": "radv: fix 16-bit support in radv_lower_vs_input",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "b366fef091d33e7d5307f292b2320267c841e350"
},

5
src/amd/vulkan/radv_pipeline.c
View file

@ -4241,9 +4241,10 @@ radv_lower_vs_input(nir_shader *nir, const struct radv_pipeline_key *pipeline_ke
if (swizzle[i + component] < num_channels) {
channels[i] = nir_channel(&b, &intrin->dest.ssa, swizzle[idx]);
} else if (i + component == 3) {
channels[i] = is_float ? nir_imm_float(&b, 1.0f) : nir_imm_int(&b, 1u);
channels[i] = is_float ? nir_imm_floatN_t(&b, 1.0f, intrin->dest.ssa.bit_size)
: nir_imm_intN_t(&b, 1u, intrin->dest.ssa.bit_size);
} else {
channels[i] = nir_imm_zero(&b, 1, 32);
channels[i] = nir_imm_zero(&b, 1, intrin->dest.ssa.bit_size);
}
}