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radeonsi/vcn: Support H264 encode weighted_bipred_idc

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Only default (0) and implicit (2) are supported, explicit (1) is not.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33846>
This commit is contained in:
David Rosca 2025-03-03 13:44:33 +01:00 • committed by Marge Bot
parent 0ec174afd5
commit 3ea3aa0f90
2 changed files with 4 additions and 2 deletions
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4
src/gallium/drivers/radeonsi/radeon_vcn_enc.c
View file

@ -296,7 +296,9 @@ static void radeon_vcn_enc_h264_get_spec_misc_param(struct radeon_encoder *enc,
pic->pic_ctrl.constrained_intra_pred_flag;
enc->enc_pic.spec_misc.half_pel_enabled = 1;
enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
enc->enc_pic.spec_misc.weighted_bipred_idc = 0;
enc->enc_pic.spec_misc.weighted_bipred_idc =
pic->pic_ctrl.weighted_bipred_idc != 1 ?
pic->pic_ctrl.weighted_bipred_idc : 0;
enc->enc_pic.spec_misc.transform_8x8_mode =
sscreen->info.vcn_ip_version >= VCN_5_0_0 &&
pic->pic_ctrl.transform_8x8_mode_flag;

2
src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c
View file

@ -440,7 +440,7 @@ unsigned int radeon_enc_write_pps(struct radeon_encoder *enc, uint8_t nal_byte,
radeon_bs_code_ue(&bs, enc->enc_pic.h264.desc->pic_ctrl.num_ref_idx_l0_default_active_minus1);
radeon_bs_code_ue(&bs, enc->enc_pic.h264.desc->pic_ctrl.num_ref_idx_l1_default_active_minus1);
radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* weighted_pred_flag */
radeon_bs_code_fixed_bits(&bs, 0x0, 2); /* weighted_bipred_idc */
radeon_bs_code_fixed_bits(&bs, enc->enc_pic.spec_misc.weighted_bipred_idc, 2);
radeon_bs_code_se(&bs, 0x0); /* pic_init_qp_minus26 */
radeon_bs_code_se(&bs, 0x0); /* pic_init_qs_minus26 */
radeon_bs_code_se(&bs, enc->enc_pic.h264_deblock.cb_qp_offset); /* chroma_qp_index_offset */