From 3ea3aa0f904ea96d75d717a36b7604a122f7bae4 Mon Sep 17 00:00:00 2001 From: David Rosca Date: Mon, 3 Mar 2025 13:44:33 +0100 Subject: [PATCH] radeonsi/vcn: Support H264 encode weighted_bipred_idc Only default (0) and implicit (2) are supported, explicit (1) is not. Reviewed-by: Ruijing Dong Part-of: --- src/gallium/drivers/radeonsi/radeon_vcn_enc.c | 4 +++- src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc.c index 591d4d34f62..c0ac554f007 100644 --- a/src/gallium/drivers/radeonsi/radeon_vcn_enc.c +++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc.c @@ -296,7 +296,9 @@ static void radeon_vcn_enc_h264_get_spec_misc_param(struct radeon_encoder *enc, pic->pic_ctrl.constrained_intra_pred_flag; enc->enc_pic.spec_misc.half_pel_enabled = 1; enc->enc_pic.spec_misc.quarter_pel_enabled = 1; - enc->enc_pic.spec_misc.weighted_bipred_idc = 0; + enc->enc_pic.spec_misc.weighted_bipred_idc = + pic->pic_ctrl.weighted_bipred_idc != 1 ? + pic->pic_ctrl.weighted_bipred_idc : 0; enc->enc_pic.spec_misc.transform_8x8_mode = sscreen->info.vcn_ip_version >= VCN_5_0_0 && pic->pic_ctrl.transform_8x8_mode_flag; diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c index 554c549ee42..0e989d311ae 100644 --- a/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c +++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c @@ -440,7 +440,7 @@ unsigned int radeon_enc_write_pps(struct radeon_encoder *enc, uint8_t nal_byte, radeon_bs_code_ue(&bs, enc->enc_pic.h264.desc->pic_ctrl.num_ref_idx_l0_default_active_minus1); radeon_bs_code_ue(&bs, enc->enc_pic.h264.desc->pic_ctrl.num_ref_idx_l1_default_active_minus1); radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* weighted_pred_flag */ - radeon_bs_code_fixed_bits(&bs, 0x0, 2); /* weighted_bipred_idc */ + radeon_bs_code_fixed_bits(&bs, enc->enc_pic.spec_misc.weighted_bipred_idc, 2); radeon_bs_code_se(&bs, 0x0); /* pic_init_qp_minus26 */ radeon_bs_code_se(&bs, 0x0); /* pic_init_qs_minus26 */ radeon_bs_code_se(&bs, enc->enc_pic.h264_deblock.cb_qp_offset); /* chroma_qp_index_offset */