brw: Apply Gfx9 vgrf127 workaround in more cases

No shader-db changes on any Intel platform.

fossil-db:

Skylake
Intel(R) HD Graphics 530 (SKL GT2)
Totals:
Cycle count: 57669758527 -> 57669757913 (-0.00%); split: -0.00%, +0.00%

Totals from 10 (0.00% of 1736875) affected shaders:
Cycle count: 274949 -> 274335 (-0.22%); split: -0.36%, +0.14%

This change is likely due to subtle differences of different registers
being allocated.

In addition, fossils/google-meet-clvk/BgBlur.1f58fdf742c27594.1.foz and
fossils/google-meet-clvk/Relight.1f58fdf742c27594.1.foz stopped failing
EU validation on Gfx9 platforms.

Closes: #14171
Fixes: e7b7d572b3 ("intel/fs/ra: Re-arrange interference setup")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38122>

src/intel/compiler/brw/brw_reg_allocate.cpp

@@ -602,10 +602,13 @@ brw_reg_alloc::setup_inst_interference(const brw_inst *inst)
        * This node has a fixed assignment to grf127.
        *
        * We don't apply it to SIMD16 instructions because previous code avoids
-       * any register overlap between sources and destination.
+       * any register overlap between sources and destination. Some care is
+       * taken to detect when interference may not have been added between
+       * source and destination. This can occur in SIMD16 with UW
+       * destination. See also gitlab issue #14171.
        */
       if (inst->opcode == SHADER_OPCODE_SEND && inst->dst.file == VGRF &&
-          inst->exec_size < 16)
+          (inst->exec_size < 16 || brw_type_size_bytes(inst->dst.type) < 4))
          ra_add_node_interference(g, first_vgrf_node + inst->dst.nr,
                                      grf127_send_hack_node);
    }