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https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-03-12 13:20:33 +01:00
etnaviv: isa: Restrict COND field to conditional instructions
Move the COND field (bits 6-10) out of the root #instruction bitset so only instructions that actually support conditions decode/encode it. Non-conditional instructions now enforce those bits as zero via a pattern. This follows the freedreno ir3 precedent where conditional and non-conditional instruction variants use separate intermediate bitsets. Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40205>
This commit is contained in:
Christian Gmeiner
Marge Bot
parent
b442dc23fd
commit
3d802672f8
2 changed files with 148 additions and 12 deletions
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@ -7,6 +7,10 @@ SPDX-License-Identifier: MIT
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<isa>
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<template name="INSTR_ALU">
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{NAME}{DST_FULL}{SAT}{SKPHP}{UNK}{TYPE}{PMODE}{THREAD}{RMODE}
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</template>
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<template name="INSTR_ALU_COND">
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{NAME}{DST_FULL}{SAT}{COND}{SKPHP}{UNK}{TYPE}{PMODE}{THREAD}{RMODE}
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</template>
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@ -15,11 +19,15 @@ SPDX-License-Identifier: MIT
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</template>
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<template name="INSTR_CF">
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{NAME}{TYPE}
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</template>
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<template name="INSTR_CF_COND">
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{NAME}{COND}{TYPE}
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</template>
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<template name="INSTR_LOAD_STORE">
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{NAME}{SAT}{COND}{SKPHP}{DENORM}{LOCAL}{TYPE}{LEFT_SHIFT}{PMODE}
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{NAME}{SAT}{SKPHP}{DENORM}{LOCAL}{TYPE}{LEFT_SHIFT}{PMODE}
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</template>
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<enum name="#cond">
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@ -131,7 +139,6 @@ SPDX-License-Identifier: MIT
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</bitset>
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<bitset name="#instruction" size="128">
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<field name="COND" low="6" high="10" type="#cond"/>
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<field name="SAT" pos="11" type="bool" display=".sat"/>
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<field name="TYPE_BIT2" pos="53" type="uint"/>
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@ -146,7 +153,6 @@ SPDX-License-Identifier: MIT
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<map name="TYPE_BIT2">(src->type & 0x4) > 2</map>
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<map name="LOW_HALF">(src->thread & 0x1)</map>
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<map name="HIGH_HALF">(src->thread & 0x2) > 1</map>
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<map name="COND">src->cond</map>
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<map name="RMODE">src->rounding</map>
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<map name="SAT">src->sat</map>
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<map name="PMODE">!src->pmode</map>
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@ -334,6 +340,8 @@ SPDX-License-Identifier: MIT
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</bitset>
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<bitset name="#instruction-alu-no-src" extends="#instruction-alu">
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<pattern low="6" high="10">00000</pattern>
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<display>
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{NAME} {DST:align=18}{DST_FULL}, void, void, void
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</display>
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@ -380,6 +388,13 @@ SPDX-License-Identifier: MIT
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<bitset name="#instruction-alu-no-dst-maybe-src0-src1" extends="#instruction-alu">
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<doc>Needed for texkill</doc>
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<field name="COND" low="6" high="10" type="#cond"/>
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<encode type="struct etna_inst *" case-prefix="ISA_OPC_">
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<map name="COND">src->cond</map>
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</encode>
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<display>
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{NAME}{COND}{TYPE}{PMODE}{THREAD}{RMODE} {DST:align=18}{DST_FULL}, void, void, void
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</display>
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@ -430,6 +445,7 @@ SPDX-License-Identifier: MIT
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<bitset name="#instruction-alu-src0" extends="#instruction-alu">
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<meta has_dest="true" valid_srcs="0"/>
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<pattern low="6" high="10">00000</pattern>
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<display>
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{INSTR_ALU} {DST:align=18}, {SRC0}, void, void
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@ -467,6 +483,7 @@ SPDX-License-Identifier: MIT
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<bitset name="#instruction-alu-src2" extends="#instruction-alu">
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<meta has_dest="true" valid_srcs="2"/>
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<pattern low="6" high="10">00000</pattern>
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<display>
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{INSTR_ALU} {DST:align=18}, void, void, {SRC2}
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@ -512,6 +529,7 @@ SPDX-License-Identifier: MIT
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<bitset name="#instruction-alu-src0-src1" extends="#instruction-alu">
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<meta has_dest="true" valid_srcs="0|1"/>
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<pattern low="6" high="10">00000</pattern>
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<display>
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{INSTR_ALU} {DST:align=18}, {SRC0}, {SRC1}, void
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@ -549,8 +567,54 @@ SPDX-License-Identifier: MIT
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<pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP -->
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</bitset>
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<bitset name="#instruction-alu-cond-src0-src1" extends="#instruction-alu">
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<meta type="alu_cond" has_dest="true" valid_srcs="0|1"/>
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<field name="COND" low="6" high="10" type="#cond"/>
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<display>
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{INSTR_ALU_COND} {DST:align=18}, {SRC0}, {SRC1}, void
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</display>
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<!-- SRC0 -->
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<pattern pos="43">1</pattern> <!-- SRC0_USE -->
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<field name="SRC0_REG" low="44" high="52" type="uint"/>
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<field name="SRC0" low="54" high="63" type="#instruction-src">
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<param name="SRC0_REG" as="SRC_REG"/>
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<param name="SRC0_AMODE" as="SRC_AMODE"/>
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<param name="SRC0_RGROUP" as="SRC_RGROUP"/>
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</field>
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<field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/>
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<field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/>
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<!-- SRC1 -->
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<pattern pos="70">1</pattern> <!-- SRC1_USE -->
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<field name="SRC1_REG" low="71" high="79" type="uint"/>
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<field name="SRC1" low="81" high="90" type="#instruction-src">
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<param name="SRC1_REG" as="SRC_REG"/>
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<param name="SRC1_AMODE" as="SRC_AMODE"/>
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<param name="SRC1_RGROUP" as="SRC_RGROUP"/>
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</field>
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<field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/>
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<field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/>
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<!-- SRC2 -->
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<pattern pos="99">0</pattern> <!-- SRC2_USE -->
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<pattern low="100" high="108">000000000</pattern> <!-- SRC2_REG -->
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<pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ -->
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<pattern pos="118">0</pattern> <!-- SRC2_NEG -->
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<pattern pos="119">0</pattern> <!-- SRC2_ABS -->
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<pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE -->
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<pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP -->
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<encode type="struct etna_inst *" case-prefix="ISA_OPC_">
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<map name="COND">src->cond</map>
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</encode>
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</bitset>
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<bitset name="#instruction-alu-src0-src2" extends="#instruction-alu">
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<meta has_dest="true" valid_srcs="0|2"/>
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<pattern low="6" high="10">00000</pattern>
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<display>
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{INSTR_ALU} {DST:align=18}, {SRC0}, void, {SRC2}
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@ -598,6 +662,7 @@ SPDX-License-Identifier: MIT
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<bitset name="#instruction-alu-src1-src2" extends="#instruction-alu">
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<meta has_dest="true" valid_srcs="1|2"/>
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<pattern low="6" high="10">00000</pattern>
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<display>
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{INSTR_ALU} {DST:align=18}, void, {SRC1}, {SRC2}
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@ -650,6 +715,8 @@ SPDX-License-Identifier: MIT
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<bitset name="#instruction-alu-src0-src1-src2" extends="#instruction-alu">
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<meta has_dest="true" valid_srcs="0|1|2"/>
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<pattern low="6" high="10">00000</pattern>
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<display>
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{INSTR_ALU} {DST:align=18}, {SRC0}, {SRC1}, {SRC2}
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</display>
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@ -688,8 +755,56 @@ SPDX-License-Identifier: MIT
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<field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/>
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</bitset>
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<bitset name="#instruction-alu-cond-src0-src1-src2" extends="#instruction-alu">
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<meta type="alu_cond" has_dest="true" valid_srcs="0|1|2"/>
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<field name="COND" low="6" high="10" type="#cond"/>
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<display>
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{INSTR_ALU_COND} {DST:align=18}, {SRC0}, {SRC1}, {SRC2}
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</display>
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<!-- SRC0 -->
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<pattern pos="43">1</pattern> <!-- SRC0_USE -->
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<field name="SRC0_REG" low="44" high="52" type="uint"/>
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<field name="SRC0" low="54" high="63" type="#instruction-src">
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<param name="SRC0_REG" as="SRC_REG"/>
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<param name="SRC0_AMODE" as="SRC_AMODE"/>
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<param name="SRC0_RGROUP" as="SRC_RGROUP"/>
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</field>
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<field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/>
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<field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/>
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<!-- SRC1 -->
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<pattern pos="70">1</pattern> <!-- SRC1_USE -->
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<field name="SRC1_REG" low="71" high="79" type="uint"/>
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<field name="SRC1" low="81" high="90" type="#instruction-src">
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<param name="SRC1_REG" as="SRC_REG"/>
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<param name="SRC1_AMODE" as="SRC_AMODE"/>
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<param name="SRC1_RGROUP" as="SRC_RGROUP"/>
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</field>
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<field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/>
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<field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/>
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<!-- SRC2 -->
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<pattern pos="99">1</pattern> <!-- SRC2_USE -->
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<field name="SRC2_REG" low="100" high="108" type="uint"/>
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<field name="SRC2" low="110" high="119" type="#instruction-src">
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<param name="SRC2_REG" as="SRC_REG"/>
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<param name="SRC2_AMODE" as="SRC_AMODE"/>
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<param name="SRC2_RGROUP" as="SRC_RGROUP"/>
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</field>
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<field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/>
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<field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/>
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<encode type="struct etna_inst *" case-prefix="ISA_OPC_">
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<map name="COND">src->cond</map>
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</encode>
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</bitset>
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<bitset name="#instruction-tex" extends="#instruction">
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<meta type="tex"/>
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<pattern low="6" high="10">00000</pattern>
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<field name="DST_USE" pos="12" type="bool"/>
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<field name="DST" low="13" high="26" type="#instruction-dst">
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@ -903,6 +1018,8 @@ SPDX-License-Identifier: MIT
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</bitset>
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<bitset name="#instruction-cf-no-src" extends="#instruction-cf">
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<pattern low="6" high="10">00000</pattern>
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<display>
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{INSTR_CF} {:align=18}void, void, void, {TARGET}
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</display>
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@ -920,10 +1037,16 @@ SPDX-License-Identifier: MIT
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</expr>
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<bitset name="#instruction-cf-src0" extends="#instruction-cf">
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<meta valid_srcs="0"/>
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<meta type="cf_cond" valid_srcs="0"/>
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<field name="COND" low="6" high="10" type="#cond"/>
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<encode type="struct etna_inst *" case-prefix="ISA_OPC_">
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<map name="COND">src->cond</map>
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</encode>
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<display>
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{INSTR_CF} {:align=18}void, {SRC0}, void, {TARGET}
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{INSTR_CF_COND} {:align=18}void, {SRC0}, void, {TARGET}
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</display>
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<!-- SRC0 -->
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@ -948,10 +1071,16 @@ SPDX-License-Identifier: MIT
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</bitset>
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<bitset name="#instruction-cf-src0-src1" extends="#instruction-cf">
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<meta valid_srcs="0|1"/>
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<meta type="cf_cond" valid_srcs="0|1"/>
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<field name="COND" low="6" high="10" type="#cond"/>
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<encode type="struct etna_inst *" case-prefix="ISA_OPC_">
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<map name="COND">src->cond</map>
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</encode>
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<display>
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{INSTR_CF} {:align=18}void, {SRC0}, {SRC1}, {TARGET}
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{INSTR_CF_COND} {:align=18}void, {SRC0}, {SRC1}, {TARGET}
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</display>
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<!-- SRC0 -->
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@ -1000,6 +1129,7 @@ SPDX-License-Identifier: MIT
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<bitset name="#instruction-load" extends="#instruction">
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<meta type="load_store"/>
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<meta has_dest="true" valid_srcs="0|1"/>
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<pattern low="6" high="10">00000</pattern>
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<field name="DST_USE" pos="12" type="bool"/>
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<field name="DST" low="13" high="26" type="#instruction-dst">
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@ -1065,6 +1195,7 @@ SPDX-License-Identifier: MIT
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<bitset name="#instruction-store" extends="#instruction">
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<meta type="load_store"/>
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<meta has_dest="true" valid_srcs="0|1|2"/>
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<pattern low="6" high="10">00000</pattern>
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<pattern low="12" high="16">xxxxx</pattern>
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<pattern pos="17">x</pattern>
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@ -1195,12 +1326,12 @@ SPDX-License-Identifier: MIT
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<!-- litp -->
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<bitset name="select" extends="#instruction-alu-src0-src1-src2">
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<bitset name="select" extends="#instruction-alu-cond-src0-src1-src2">
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<pattern low="0" high="5">001111</pattern> <!-- OPC -->
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<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
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</bitset>
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<bitset name="set" extends="#instruction-alu-src0-src1">
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<bitset name="set" extends="#instruction-alu-cond-src0-src1">
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<pattern low="0" high="5">010000</pattern> <!-- OPC -->
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<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
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</bitset>
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@ -1354,7 +1485,7 @@ SPDX-License-Identifier: MIT
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<!-- f2i7 -->
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<bitset name="cmp" extends="#instruction-alu-src0-src1-src2">
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<bitset name="cmp" extends="#instruction-alu-cond-src0-src1-src2">
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<pattern low="0" high="5">110001</pattern> <!-- OPC -->
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<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
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</bitset>
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@ -1589,6 +1720,7 @@ SPDX-License-Identifier: MIT
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<bitset name="#extended-instruction-alu" extends="#instruction-alu">
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<pattern low="0" high="5">111111</pattern> <!-- OPC -->
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<pattern low="6" high="10">00000</pattern>
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<pattern pos="80">1</pattern> <!-- OPCODE_BIT6 -->
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</bitset>
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@ -324,7 +324,11 @@ fn generate_peg_grammar_instructions(isa: &ISA) -> String {
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rule_parts.push("TexSrc ~ \",\"".to_string());
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}
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let possible_srcs = if type_ == "cf" { 2 } else { 3 };
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let possible_srcs = if matches!(type_, "cf" | "cf_cond") {
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2
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} else {
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3
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};
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let valid_srcs: Vec<_> = meta
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.get("valid_srcs")
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.unwrap_or(&"")
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@ -343,7 +347,7 @@ fn generate_peg_grammar_instructions(isa: &ISA) -> String {
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}
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}
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if type_ == "cf" {
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if matches!(type_, "cf" | "cf_cond") {
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rule_parts.push("\",\"".to_string());
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rule_parts.push("Target".to_string());
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}
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