diff --git a/src/etnaviv/isa/etnaviv.xml b/src/etnaviv/isa/etnaviv.xml
index f123e7edce8..6f4fa0a79aa 100644
--- a/src/etnaviv/isa/etnaviv.xml
+++ b/src/etnaviv/isa/etnaviv.xml
@@ -7,6 +7,10 @@ SPDX-License-Identifier: MIT
 <isa>
 
 <template name="INSTR_ALU">
+	{NAME}{DST_FULL}{SAT}{SKPHP}{UNK}{TYPE}{PMODE}{THREAD}{RMODE}
+</template>
+
+<template name="INSTR_ALU_COND">
 	{NAME}{DST_FULL}{SAT}{COND}{SKPHP}{UNK}{TYPE}{PMODE}{THREAD}{RMODE}
 </template>
 
@@ -15,11 +19,15 @@ SPDX-License-Identifier: MIT
 </template>
 
 <template name="INSTR_CF">
+	{NAME}{TYPE}
+</template>
+
+<template name="INSTR_CF_COND">
 	{NAME}{COND}{TYPE}
 </template>
 
 <template name="INSTR_LOAD_STORE">
-	{NAME}{SAT}{COND}{SKPHP}{DENORM}{LOCAL}{TYPE}{LEFT_SHIFT}{PMODE}
+	{NAME}{SAT}{SKPHP}{DENORM}{LOCAL}{TYPE}{LEFT_SHIFT}{PMODE}
 </template>
 
 <enum name="#cond">
@@ -131,7 +139,6 @@ SPDX-License-Identifier: MIT
 </bitset>
 
 <bitset name="#instruction" size="128">
-	<field name="COND" low="6" high="10" type="#cond"/>
 	<field name="SAT" pos="11" type="bool" display=".sat"/>
 
 	<field name="TYPE_BIT2" pos="53" type="uint"/>
@@ -146,7 +153,6 @@ SPDX-License-Identifier: MIT
 		<map name="TYPE_BIT2">(src->type &amp; 0x4) &gt; 2</map>
 		<map name="LOW_HALF">(src->thread &amp; 0x1)</map>
 		<map name="HIGH_HALF">(src->thread &amp; 0x2) &gt; 1</map>
-		<map name="COND">src->cond</map>
 		<map name="RMODE">src->rounding</map>
 		<map name="SAT">src->sat</map>
 		<map name="PMODE">!src->pmode</map>
@@ -334,6 +340,8 @@ SPDX-License-Identifier: MIT
 </bitset>
 
 <bitset name="#instruction-alu-no-src" extends="#instruction-alu">
+	<pattern low="6" high="10">00000</pattern>
+
 	<display>
 		{NAME} {DST:align=18}{DST_FULL}, void, void, void
 	</display>
@@ -380,6 +388,13 @@ SPDX-License-Identifier: MIT
 
 <bitset name="#instruction-alu-no-dst-maybe-src0-src1" extends="#instruction-alu">
 	<doc>Needed for texkill</doc>
+
+	<field name="COND" low="6" high="10" type="#cond"/>
+
+	<encode type="struct etna_inst *" case-prefix="ISA_OPC_">
+		<map name="COND">src->cond</map>
+	</encode>
+
 	<display>
 		{NAME}{COND}{TYPE}{PMODE}{THREAD}{RMODE} {DST:align=18}{DST_FULL}, void, void, void
 	</display>
@@ -430,6 +445,7 @@ SPDX-License-Identifier: MIT
 
 <bitset name="#instruction-alu-src0" extends="#instruction-alu">
 	<meta has_dest="true" valid_srcs="0"/>
+	<pattern low="6" high="10">00000</pattern>
 
 	<display>
 		{INSTR_ALU} {DST:align=18}, {SRC0}, void, void
@@ -467,6 +483,7 @@ SPDX-License-Identifier: MIT
 
 <bitset name="#instruction-alu-src2" extends="#instruction-alu">
 	<meta has_dest="true" valid_srcs="2"/>
+	<pattern low="6" high="10">00000</pattern>
 
 	<display>
 		{INSTR_ALU} {DST:align=18}, void, void, {SRC2}
@@ -512,6 +529,7 @@ SPDX-License-Identifier: MIT
 
 <bitset name="#instruction-alu-src0-src1" extends="#instruction-alu">
 	<meta has_dest="true" valid_srcs="0|1"/>
+	<pattern low="6" high="10">00000</pattern>
 
 	<display>
 		{INSTR_ALU} {DST:align=18}, {SRC0}, {SRC1}, void
@@ -549,8 +567,54 @@ SPDX-License-Identifier: MIT
 	<pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP -->
 </bitset>
 
+<bitset name="#instruction-alu-cond-src0-src1" extends="#instruction-alu">
+	<meta type="alu_cond" has_dest="true" valid_srcs="0|1"/>
+
+	<field name="COND" low="6" high="10" type="#cond"/>
+
+	<display>
+		{INSTR_ALU_COND} {DST:align=18}, {SRC0}, {SRC1}, void
+	</display>
+
+	<!-- SRC0 -->
+	<pattern pos="43">1</pattern> <!-- SRC0_USE -->
+	<field name="SRC0_REG" low="44" high="52" type="uint"/>
+	<field name="SRC0" low="54" high="63" type="#instruction-src">
+		<param name="SRC0_REG" as="SRC_REG"/>
+		<param name="SRC0_AMODE" as="SRC_AMODE"/>
+		<param name="SRC0_RGROUP" as="SRC_RGROUP"/>
+	</field>
+	<field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/>
+	<field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/>
+
+	<!-- SRC1 -->
+	<pattern pos="70">1</pattern> <!-- SRC1_USE -->
+	<field name="SRC1_REG" low="71" high="79" type="uint"/>
+	<field name="SRC1" low="81" high="90" type="#instruction-src">
+		<param name="SRC1_REG" as="SRC_REG"/>
+		<param name="SRC1_AMODE" as="SRC_AMODE"/>
+		<param name="SRC1_RGROUP" as="SRC_RGROUP"/>
+	</field>
+	<field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/>
+	<field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/>
+
+	<!-- SRC2 -->
+	<pattern pos="99">0</pattern> <!-- SRC2_USE -->
+	<pattern low="100" high="108">000000000</pattern> <!-- SRC2_REG -->
+	<pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ -->
+	<pattern pos="118">0</pattern> <!-- SRC2_NEG -->
+	<pattern pos="119">0</pattern> <!-- SRC2_ABS -->
+	<pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE -->
+	<pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP -->
+
+	<encode type="struct etna_inst *" case-prefix="ISA_OPC_">
+		<map name="COND">src->cond</map>
+	</encode>
+</bitset>
+
 <bitset name="#instruction-alu-src0-src2" extends="#instruction-alu">
 	<meta has_dest="true" valid_srcs="0|2"/>
+	<pattern low="6" high="10">00000</pattern>
 
 	<display>
 		{INSTR_ALU} {DST:align=18}, {SRC0}, void, {SRC2}
@@ -598,6 +662,7 @@ SPDX-License-Identifier: MIT
 
 <bitset name="#instruction-alu-src1-src2" extends="#instruction-alu">
 	<meta has_dest="true" valid_srcs="1|2"/>
+	<pattern low="6" high="10">00000</pattern>
 
 	<display>
 		{INSTR_ALU} {DST:align=18}, void, {SRC1}, {SRC2}
@@ -650,6 +715,8 @@ SPDX-License-Identifier: MIT
 
 <bitset name="#instruction-alu-src0-src1-src2" extends="#instruction-alu">
 	<meta has_dest="true" valid_srcs="0|1|2"/>
+	<pattern low="6" high="10">00000</pattern>
+
 	<display>
 		{INSTR_ALU} {DST:align=18}, {SRC0}, {SRC1}, {SRC2}
 	</display>
@@ -688,8 +755,56 @@ SPDX-License-Identifier: MIT
 	<field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/>
 </bitset>
 
+<bitset name="#instruction-alu-cond-src0-src1-src2" extends="#instruction-alu">
+	<meta type="alu_cond" has_dest="true" valid_srcs="0|1|2"/>
+
+	<field name="COND" low="6" high="10" type="#cond"/>
+
+	<display>
+		{INSTR_ALU_COND} {DST:align=18}, {SRC0}, {SRC1}, {SRC2}
+	</display>
+
+	<!-- SRC0 -->
+	<pattern pos="43">1</pattern> <!-- SRC0_USE -->
+	<field name="SRC0_REG" low="44" high="52" type="uint"/>
+	<field name="SRC0" low="54" high="63" type="#instruction-src">
+		<param name="SRC0_REG" as="SRC_REG"/>
+		<param name="SRC0_AMODE" as="SRC_AMODE"/>
+		<param name="SRC0_RGROUP" as="SRC_RGROUP"/>
+	</field>
+	<field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/>
+	<field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/>
+
+	<!-- SRC1 -->
+	<pattern pos="70">1</pattern> <!-- SRC1_USE -->
+	<field name="SRC1_REG" low="71" high="79" type="uint"/>
+	<field name="SRC1" low="81" high="90" type="#instruction-src">
+		<param name="SRC1_REG" as="SRC_REG"/>
+		<param name="SRC1_AMODE" as="SRC_AMODE"/>
+		<param name="SRC1_RGROUP" as="SRC_RGROUP"/>
+	</field>
+	<field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/>
+	<field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/>
+
+	<!-- SRC2 -->
+	<pattern pos="99">1</pattern> <!-- SRC2_USE -->
+	<field name="SRC2_REG" low="100" high="108" type="uint"/>
+	<field name="SRC2" low="110" high="119" type="#instruction-src">
+		<param name="SRC2_REG" as="SRC_REG"/>
+		<param name="SRC2_AMODE" as="SRC_AMODE"/>
+		<param name="SRC2_RGROUP" as="SRC_RGROUP"/>
+	</field>
+	<field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/>
+	<field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/>
+
+	<encode type="struct etna_inst *" case-prefix="ISA_OPC_">
+		<map name="COND">src->cond</map>
+	</encode>
+</bitset>
+
 <bitset name="#instruction-tex" extends="#instruction">
 	<meta type="tex"/>
+	<pattern low="6" high="10">00000</pattern>
 
 	<field name="DST_USE" pos="12" type="bool"/>
 	<field name="DST" low="13" high="26" type="#instruction-dst">
@@ -903,6 +1018,8 @@ SPDX-License-Identifier: MIT
 </bitset>
 
 <bitset name="#instruction-cf-no-src" extends="#instruction-cf">
+	<pattern low="6" high="10">00000</pattern>
+
 	<display>
 		{INSTR_CF} {:align=18}void, void, void, {TARGET}
 	</display>
@@ -920,10 +1037,16 @@ SPDX-License-Identifier: MIT
 </expr>
 
 <bitset name="#instruction-cf-src0" extends="#instruction-cf">
-	<meta valid_srcs="0"/>
+	<meta type="cf_cond" valid_srcs="0"/>
+
+	<field name="COND" low="6" high="10" type="#cond"/>
+
+	<encode type="struct etna_inst *" case-prefix="ISA_OPC_">
+		<map name="COND">src->cond</map>
+	</encode>
 
        <display>
-               {INSTR_CF} {:align=18}void, {SRC0}, void, {TARGET}
+               {INSTR_CF_COND} {:align=18}void, {SRC0}, void, {TARGET}
        </display>
 
        <!-- SRC0 -->
@@ -948,10 +1071,16 @@ SPDX-License-Identifier: MIT
 </bitset>
 
 <bitset name="#instruction-cf-src0-src1" extends="#instruction-cf">
-	<meta valid_srcs="0|1"/>
+	<meta type="cf_cond" valid_srcs="0|1"/>
+
+	<field name="COND" low="6" high="10" type="#cond"/>
+
+	<encode type="struct etna_inst *" case-prefix="ISA_OPC_">
+		<map name="COND">src->cond</map>
+	</encode>
 
 	<display>
-		{INSTR_CF} {:align=18}void, {SRC0}, {SRC1}, {TARGET}
+		{INSTR_CF_COND} {:align=18}void, {SRC0}, {SRC1}, {TARGET}
 	</display>
 
 	<!-- SRC0 -->
@@ -1000,6 +1129,7 @@ SPDX-License-Identifier: MIT
 <bitset name="#instruction-load" extends="#instruction">
 	<meta type="load_store"/>
 	<meta has_dest="true" valid_srcs="0|1"/>
+	<pattern low="6" high="10">00000</pattern>
 
 	<field name="DST_USE" pos="12" type="bool"/>
 	<field name="DST" low="13" high="26" type="#instruction-dst">
@@ -1065,6 +1195,7 @@ SPDX-License-Identifier: MIT
 <bitset name="#instruction-store" extends="#instruction">
 	<meta type="load_store"/>
 	<meta has_dest="true" valid_srcs="0|1|2"/>
+	<pattern low="6" high="10">00000</pattern>
 
 	<pattern low="12" high="16">xxxxx</pattern>
 	<pattern pos="17">x</pattern>
@@ -1195,12 +1326,12 @@ SPDX-License-Identifier: MIT
 
 <!-- litp -->
 
-<bitset name="select" extends="#instruction-alu-src0-src1-src2">
+<bitset name="select" extends="#instruction-alu-cond-src0-src1-src2">
 	<pattern low="0" high="5">001111</pattern> <!-- OPC -->
 	<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
 </bitset>
 
-<bitset name="set" extends="#instruction-alu-src0-src1">
+<bitset name="set" extends="#instruction-alu-cond-src0-src1">
 	<pattern low="0" high="5">010000</pattern> <!-- OPC -->
 	<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
 </bitset>
@@ -1354,7 +1485,7 @@ SPDX-License-Identifier: MIT
 
 <!-- f2i7 -->
 
-<bitset name="cmp" extends="#instruction-alu-src0-src1-src2">
+<bitset name="cmp" extends="#instruction-alu-cond-src0-src1-src2">
 	<pattern low="0" high="5">110001</pattern> <!-- OPC -->
 	<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
 </bitset>
@@ -1589,6 +1720,7 @@ SPDX-License-Identifier: MIT
 
 <bitset name="#extended-instruction-alu" extends="#instruction-alu">
 	<pattern low="0" high="5">111111</pattern> <!-- OPC -->
+	<pattern low="6" high="10">00000</pattern>
 	<pattern pos="80">1</pattern> <!-- OPCODE_BIT6 -->
 </bitset>
 
diff --git a/src/etnaviv/isa/isa_proc.rs b/src/etnaviv/isa/isa_proc.rs
index 2df62d5bcf9..d3c8ab03578 100644
--- a/src/etnaviv/isa/isa_proc.rs
+++ b/src/etnaviv/isa/isa_proc.rs
@@ -324,7 +324,11 @@ fn generate_peg_grammar_instructions(isa: &ISA) -> String {
             rule_parts.push("TexSrc ~ \",\"".to_string());
         }
 
-        let possible_srcs = if type_ == "cf" { 2 } else { 3 };
+        let possible_srcs = if matches!(type_, "cf" | "cf_cond") {
+            2
+        } else {
+            3
+        };
         let valid_srcs: Vec<_> = meta
             .get("valid_srcs")
             .unwrap_or(&"")
@@ -343,7 +347,7 @@ fn generate_peg_grammar_instructions(isa: &ISA) -> String {
             }
         }
 
-        if type_ == "cf" {
+        if matches!(type_, "cf" | "cf_cond") {
             rule_parts.push("\",\"".to_string());
             rule_parts.push("Target".to_string());
         }