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freedreno/regs: Rename BINNING bit to FS_DISABLE in a few regs

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In most cases it is used in binning, but it is also used when
FS is empty in order to signal that FS shouldn't be invoked.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33735>
This commit is contained in:
Danylo Piliaiev 2025-02-25 13:02:24 +01:00
parent aa8fec638f
commit 3d76f307b6
7 changed files with 13 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/freedreno/.gitlab-ci/reference/fd-clouds.log
View file

@ -325,7 +325,7 @@ cmdstream[0]: 1023 dwords
{ TRACKER = TRACK_RENDER_CNTL }
{ 1 = 0x8801 }
{ 2 = 0x90 }
RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | BINNING | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 }
RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | FS_DISABLE | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 }
0000000001d91370: 0000: 706d8003 00000002 00008801 00000090
write GRAS_SC_WINDOW_SCISSOR_TL (80f0)
GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
@ -954,7 +954,7 @@ cmdstream[0]: 1023 dwords
!+ 059f086f GRAS_2D_RESOLVE_CNTL_2: { X = 2159 | Y = 1439 }
!+ 00000880 GRAS_DBG_ECO_CNTL: { UNK7 | LRZCACHELOCKDIS }
!+ 06041e11 RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = BINNING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
!+ 00000090 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | BINNING | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 }
!+ 00000090 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | FS_DISABLE | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 }
+ 00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
!+ 00000004 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
+ 00000000 RB_SAMPLE_CONFIG: { 0 }

11
src/freedreno/registers/adreno/a6xx.xml
View file

@ -3543,8 +3543,7 @@ to upconvert to 32b float internally?
<reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A6XX" usage="rp_blit">
<bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/>
<bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/>
<!-- set during binning pass: -->
<bitfield name="BINNING" pos="7" type="boolean"/>
<bitfield name="FS_DISABLE" pos="7" type="boolean"/>
<bitfield name="UNK8" low="8" high="10"/>
<bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/>
<bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/>
@ -3557,15 +3556,14 @@ to upconvert to 32b float internally?
</reg32>
<reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A7XX-" usage="rp_blit">
<bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/>
<!-- set during binning pass: -->
<bitfield name="BINNING" pos="7" type="boolean"/>
<bitfield name="FS_DISABLE" pos="7" type="boolean"/>
<bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/>
<bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/>
<bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/>
<bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/>
</reg32>
<reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" variants="A7XX-" usage="rp_blit">
<bitfield name="BINNING" pos="7" type="boolean"/>
<bitfield name="FS_DISABLE" pos="7" type="boolean"/>
</reg32>
<reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL" usage="rp_blit">
@ -5525,8 +5523,7 @@ to upconvert to 32b float internally?
<reg32 offset="0xa898" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>
<reg32 offset="0xa9aa" name="HLSQ_FS_UNKNOWN_A9AA" variants="A7XX-" usage="rp_blit">
<!-- Tentatively named, appears to disable consts being loaded via CP_LOAD_STATE6_FRAG -->
<bitfield name="CONSTS_LOAD_DISABLE" pos="0" type="boolean"/>
<bitfield name="FS_DISABLE" pos="0" type="boolean"/>
</reg32>
<reg32 offset="0xa9ac" name="SP_DITHER_CNTL" variants="A7XX-" usage="cmd">

2
src/freedreno/vulkan/tu_clear_blit.cc
View file

@ -929,7 +929,7 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum r3d_type type,
if (CHIP >= A7XX) {
tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2));
tu_cs_emit_regs(cs, A7XX_HLSQ_FS_UNKNOWN_A9AA(.consts_load_disable = false));
tu_cs_emit_regs(cs, A7XX_HLSQ_FS_UNKNOWN_A9AA(.fs_disable = false));
}
/* REPL_MODE for varying with RECTLIST (2 vertices only) */

2
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -642,7 +642,7 @@ tu6_emit_render_cntl<A6XX>(struct tu_cmd_buffer *cmd,
if (binning) {
if (no_track)
return;
cntl |= A6XX_RB_RENDER_CNTL_BINNING;
cntl |= A6XX_RB_RENDER_CNTL_FS_DISABLE;
} else {
uint32_t mrts_ubwc_enable = 0;
for (uint32_t i = 0; i < subpass->color_count; ++i) {

2
src/freedreno/vulkan/tu_shader.cc
View file

@ -2079,7 +2079,7 @@ tu6_emit_fs(struct tu_cs *cs,
if (CHIP >= A7XX) {
tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2));
tu_cs_emit_regs(cs, A7XX_HLSQ_FS_UNKNOWN_A9AA(.consts_load_disable = false));
tu_cs_emit_regs(cs, A7XX_HLSQ_FS_UNKNOWN_A9AA(.fs_disable = false));
}
if (fs) {

6
src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
View file

@ -496,14 +496,14 @@ update_render_cntl(struct fd_batch *batch, struct pipe_framebuffer_state *pfb,
OUT_REG(ring,
RB_RENDER_CNTL(
CHIP,
.binning = binning,
.fs_disable = binning,
.raster_mode = TYPE_TILED,
.raster_direction = LR_TB
)
);
OUT_REG(ring,
A7XX_GRAS_SU_RENDER_CNTL(
.binning = binning,
.fs_disable = binning,
)
);
return;
@ -534,7 +534,7 @@ update_render_cntl(struct fd_batch *batch, struct pipe_framebuffer_state *pfb,
struct fd_reg_pair rb_render_cntl = RB_RENDER_CNTL(
CHIP,
.ccusinglecachelinesize = 2,
.binning = binning,
.fs_disable = binning,
.flag_depth = depth_ubwc_enable,
.flag_mrts = mrts_ubwc_enable,
);

2
src/gallium/drivers/freedreno/a6xx/fd6_program.cc
View file

@ -836,7 +836,7 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
if (CHIP >= A7XX) {
OUT_REG(ring, A6XX_GRAS_UNKNOWN_8110(0x2));
OUT_REG(ring, A7XX_HLSQ_FS_UNKNOWN_A9AA(.consts_load_disable = false));
OUT_REG(ring, A7XX_HLSQ_FS_UNKNOWN_A9AA(.fs_disable = false));
}
OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);