From 3d76f307b6ce81c96d3207cf9207e8e03164c1c4 Mon Sep 17 00:00:00 2001 From: Danylo Piliaiev Date: Tue, 25 Feb 2025 13:02:24 +0100 Subject: [PATCH] freedreno/regs: Rename BINNING bit to FS_DISABLE in a few regs In most cases it is used in binning, but it is also used when FS is empty in order to signal that FS shouldn't be invoked. Signed-off-by: Danylo Piliaiev Part-of: --- src/freedreno/.gitlab-ci/reference/fd-clouds.log | 4 ++-- src/freedreno/registers/adreno/a6xx.xml | 11 ++++------- src/freedreno/vulkan/tu_clear_blit.cc | 2 +- src/freedreno/vulkan/tu_cmd_buffer.cc | 2 +- src/freedreno/vulkan/tu_shader.cc | 2 +- src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc | 6 +++--- src/gallium/drivers/freedreno/a6xx/fd6_program.cc | 2 +- 7 files changed, 13 insertions(+), 16 deletions(-) diff --git a/src/freedreno/.gitlab-ci/reference/fd-clouds.log b/src/freedreno/.gitlab-ci/reference/fd-clouds.log index ec258b3b8ae..eef5be87a8a 100644 --- a/src/freedreno/.gitlab-ci/reference/fd-clouds.log +++ b/src/freedreno/.gitlab-ci/reference/fd-clouds.log @@ -325,7 +325,7 @@ cmdstream[0]: 1023 dwords { TRACKER = TRACK_RENDER_CNTL } { 1 = 0x8801 } { 2 = 0x90 } - RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | BINNING | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 } + RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | FS_DISABLE | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 } 0000000001d91370: 0000: 706d8003 00000002 00008801 00000090 write GRAS_SC_WINDOW_SCISSOR_TL (80f0) GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } @@ -954,7 +954,7 @@ cmdstream[0]: 1023 dwords !+ 059f086f GRAS_2D_RESOLVE_CNTL_2: { X = 2159 | Y = 1439 } !+ 00000880 GRAS_DBG_ECO_CNTL: { UNK7 | LRZCACHELOCKDIS } !+ 06041e11 RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | RENDER_MODE = BINNING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 } -!+ 00000090 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | BINNING | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 } +!+ 00000090 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | FS_DISABLE | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 } + 00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } !+ 00000004 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } + 00000000 RB_SAMPLE_CONFIG: { 0 } diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml index 81ba0bce65b..857eec8ead4 100644 --- a/src/freedreno/registers/adreno/a6xx.xml +++ b/src/freedreno/registers/adreno/a6xx.xml @@ -3543,8 +3543,7 @@ to upconvert to 32b float internally? - - + @@ -3557,15 +3556,14 @@ to upconvert to 32b float internally? - - + - + @@ -5525,8 +5523,7 @@ to upconvert to 32b float internally? - - + diff --git a/src/freedreno/vulkan/tu_clear_blit.cc b/src/freedreno/vulkan/tu_clear_blit.cc index 7d15d67536e..876bd4615d6 100644 --- a/src/freedreno/vulkan/tu_clear_blit.cc +++ b/src/freedreno/vulkan/tu_clear_blit.cc @@ -929,7 +929,7 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum r3d_type type, if (CHIP >= A7XX) { tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2)); - tu_cs_emit_regs(cs, A7XX_HLSQ_FS_UNKNOWN_A9AA(.consts_load_disable = false)); + tu_cs_emit_regs(cs, A7XX_HLSQ_FS_UNKNOWN_A9AA(.fs_disable = false)); } /* REPL_MODE for varying with RECTLIST (2 vertices only) */ diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index 2628853a9d3..4fa3fdcf0d9 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -642,7 +642,7 @@ tu6_emit_render_cntl(struct tu_cmd_buffer *cmd, if (binning) { if (no_track) return; - cntl |= A6XX_RB_RENDER_CNTL_BINNING; + cntl |= A6XX_RB_RENDER_CNTL_FS_DISABLE; } else { uint32_t mrts_ubwc_enable = 0; for (uint32_t i = 0; i < subpass->color_count; ++i) { diff --git a/src/freedreno/vulkan/tu_shader.cc b/src/freedreno/vulkan/tu_shader.cc index 0f7d3107735..35b1b5c62f4 100644 --- a/src/freedreno/vulkan/tu_shader.cc +++ b/src/freedreno/vulkan/tu_shader.cc @@ -2079,7 +2079,7 @@ tu6_emit_fs(struct tu_cs *cs, if (CHIP >= A7XX) { tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2)); - tu_cs_emit_regs(cs, A7XX_HLSQ_FS_UNKNOWN_A9AA(.consts_load_disable = false)); + tu_cs_emit_regs(cs, A7XX_HLSQ_FS_UNKNOWN_A9AA(.fs_disable = false)); } if (fs) { diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc index 309ac5006b9..7cf9e35a9a0 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc @@ -496,14 +496,14 @@ update_render_cntl(struct fd_batch *batch, struct pipe_framebuffer_state *pfb, OUT_REG(ring, RB_RENDER_CNTL( CHIP, - .binning = binning, + .fs_disable = binning, .raster_mode = TYPE_TILED, .raster_direction = LR_TB ) ); OUT_REG(ring, A7XX_GRAS_SU_RENDER_CNTL( - .binning = binning, + .fs_disable = binning, ) ); return; @@ -534,7 +534,7 @@ update_render_cntl(struct fd_batch *batch, struct pipe_framebuffer_state *pfb, struct fd_reg_pair rb_render_cntl = RB_RENDER_CNTL( CHIP, .ccusinglecachelinesize = 2, - .binning = binning, + .fs_disable = binning, .flag_depth = depth_ubwc_enable, .flag_mrts = mrts_ubwc_enable, ); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.cc b/src/gallium/drivers/freedreno/a6xx/fd6_program.cc index ba9419607ea..5798a503403 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_program.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.cc @@ -836,7 +836,7 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b) if (CHIP >= A7XX) { OUT_REG(ring, A6XX_GRAS_UNKNOWN_8110(0x2)); - OUT_REG(ring, A7XX_HLSQ_FS_UNKNOWN_A9AA(.consts_load_disable = false)); + OUT_REG(ring, A7XX_HLSQ_FS_UNKNOWN_A9AA(.fs_disable = false)); } OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);