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radeonsi/gfx11: make flat_scratch changes for compute

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make flat_scratch gen11 changes for compute

v5: optimize the code for size (Pierre-Eric)
v4: remove type cast from 64bit to 32bit (Marek Olšák)
    use radeon_set_sh_reg_seq (Marek Olšák)
    combine RSRC and scratch reg write packets (Marek Olšák)
v3: fix coding guidelines (Marek Olšák)
v2: do not skip si_resource_reference() call (Marek Olšák)

Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
This commit is contained in:
Yogesh mohan marimuthu 2021-06-15 15:05:06 +05:30 • committed by Marge Bot
parent 02367b29c7
commit 3b0bfd254f
1 changed files with 13 additions and 5 deletions
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18
src/gallium/drivers/radeonsi/si_compute.c
View file

@ -472,11 +472,12 @@ static bool si_setup_compute_scratch_buffer(struct si_context *sctx, struct si_s
} }
if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) { if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address; if (sctx->chip_class < GFX11) {
uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
return false;
if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
return false;
}
si_resource_reference(&shader->scratch_bo, sctx->compute_scratch_buffer); si_resource_reference(&shader->scratch_bo, sctx->compute_scratch_buffer);
} }
@ -550,7 +551,14 @@ static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute
radeon_begin(cs); radeon_begin(cs);
radeon_set_sh_reg(R_00B830_COMPUTE_PGM_LO, shader_va >> 8); radeon_set_sh_reg(R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
radeon_set_sh_reg_seq(R_00B848_COMPUTE_PGM_RSRC1, 2); if (sctx->chip_class >= GFX11 && shader->scratch_bo) {
radeon_set_sh_reg_seq(R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO, 4);
radeon_emit(sctx->compute_scratch_buffer->gpu_address >> 8);
radeon_emit(sctx->compute_scratch_buffer->gpu_address >> 40);
} else {
radeon_set_sh_reg_seq(R_00B848_COMPUTE_PGM_RSRC1, 2);
}
radeon_emit(config->rsrc1); radeon_emit(config->rsrc1);
radeon_emit(config->rsrc2); radeon_emit(config->rsrc2);