radeonsi/gfx11: make flat_scratch changes for graphics

gfx11 passes scratch base address using
SPI_GFX_SCRATCH_BASE_LO and _HI registers. Make the
code changes to support the same.

v5: remove type cast from 64bit to 32bit (Marek Olšák)
v4: combine scratch_memory and scratch_state atom (Marek Olšák)
v3: skip shader relocs for gfx11
v2: make atom for scratch_memory (Indrajit)

Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
This commit is contained in:
Yogesh mohan marimuthu 2021-06-15 14:52:51 +05:30 committed by Marge Bot
parent 27104ff647
commit 02367b29c7

View file

@ -3933,7 +3933,7 @@ bool si_update_spi_tmpring_size(struct si_context *sctx, unsigned bytes)
si_context_add_resource_size(sctx, &sctx->scratch_buffer->b.b);
}
if (!si_update_scratch_relocs(sctx))
if (sctx->chip_class < GFX11 && !si_update_scratch_relocs(sctx))
return false;
}
@ -4093,7 +4093,14 @@ static void si_emit_scratch_state(struct si_context *sctx)
struct radeon_cmdbuf *cs = &sctx->gfx_cs;
radeon_begin(cs);
radeon_set_context_reg(R_0286E8_SPI_TMPRING_SIZE, sctx->spi_tmpring_size);
if (sctx->chip_class >= GFX11) {
radeon_set_context_reg_seq(R_0286E8_SPI_TMPRING_SIZE, 3);
radeon_emit(sctx->spi_tmpring_size); /* SPI_TMPRING_SIZE */
radeon_emit(sctx->scratch_buffer->gpu_address >> 8); /* SPI_GFX_SCRATCH_BASE_LO */
radeon_emit(sctx->scratch_buffer->gpu_address >> 40); /* SPI_GFX_SCRATCH_BASE_HI */
} else {
radeon_set_context_reg(R_0286E8_SPI_TMPRING_SIZE, sctx->spi_tmpring_size);
}
radeon_end();
if (sctx->scratch_buffer) {