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radeonsi/gfx11: make flat_scratch changes for graphics
gfx11 passes scratch base address using SPI_GFX_SCRATCH_BASE_LO and _HI registers. Make the code changes to support the same. v5: remove type cast from 64bit to 32bit (Marek Olšák) v4: combine scratch_memory and scratch_state atom (Marek Olšák) v3: skip shader relocs for gfx11 v2: make atom for scratch_memory (Indrajit) Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
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1 changed files with 9 additions and 2 deletions
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@ -3933,7 +3933,7 @@ bool si_update_spi_tmpring_size(struct si_context *sctx, unsigned bytes)
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si_context_add_resource_size(sctx, &sctx->scratch_buffer->b.b);
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}
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if (!si_update_scratch_relocs(sctx))
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if (sctx->chip_class < GFX11 && !si_update_scratch_relocs(sctx))
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return false;
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}
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@ -4093,7 +4093,14 @@ static void si_emit_scratch_state(struct si_context *sctx)
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struct radeon_cmdbuf *cs = &sctx->gfx_cs;
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radeon_begin(cs);
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radeon_set_context_reg(R_0286E8_SPI_TMPRING_SIZE, sctx->spi_tmpring_size);
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if (sctx->chip_class >= GFX11) {
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radeon_set_context_reg_seq(R_0286E8_SPI_TMPRING_SIZE, 3);
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radeon_emit(sctx->spi_tmpring_size); /* SPI_TMPRING_SIZE */
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radeon_emit(sctx->scratch_buffer->gpu_address >> 8); /* SPI_GFX_SCRATCH_BASE_LO */
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radeon_emit(sctx->scratch_buffer->gpu_address >> 40); /* SPI_GFX_SCRATCH_BASE_HI */
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} else {
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radeon_set_context_reg(R_0286E8_SPI_TMPRING_SIZE, sctx->spi_tmpring_size);
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}
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radeon_end();
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if (sctx->scratch_buffer) {
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