fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-25 06:30:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radv: add a predicate for reflecting DCC decompression state

Browse source 
It's somehow similar to the FCE predicate.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2018-12-10 12:57:34 +01:00
parent c506eae53d
commit 3a5adc2879
5 changed files with 44 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

28
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -1059,6 +1059,11 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
}
}
if (radv_image_has_dcc(image)) {
/* Drawing with DCC enabled also compresses colorbuffers. */
radv_update_dcc_metadata(cmd_buffer, image, true);
}
}
static void
@ -1386,6 +1391,29 @@ radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
radeon_emit(cmd_buffer->cs, pred_val >> 32);
}
/**
* Update the DCC predicate to reflect the compression state.
*/
void
radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, bool value)
{
uint64_t pred_val = value;
uint64_t va = radv_buffer_get_va(image->bo);
va += image->offset + image->dcc_pred_offset;
assert(radv_image_has_dcc(image));
radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_PFP));
radeon_emit(cmd_buffer->cs, va);
radeon_emit(cmd_buffer->cs, va >> 32);
radeon_emit(cmd_buffer->cs, pred_val);
radeon_emit(cmd_buffer->cs, pred_val >> 32);
}
/**
* Update the fast clear color values if the image is bound as a color buffer.
*/

3
src/amd/vulkan/radv_image.c
View file

@ -858,7 +858,8 @@ radv_image_alloc_dcc(struct radv_image *image)
/* + 16 for storing the clear values + dcc pred */
image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
image->fce_pred_offset = image->clear_value_offset + 8;
image->size = image->dcc_offset + image->surface.dcc_size + 16;
image->dcc_pred_offset = image->clear_value_offset + 16;
image->size = image->dcc_offset + image->surface.dcc_size + 24;
image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
}

3
src/amd/vulkan/radv_meta_clear.c
View file

@ -1288,6 +1288,9 @@ uint32_t
radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, uint32_t value)
{
/* Mark the image as being compressed. */
radv_update_dcc_metadata(cmd_buffer, image, true);
return radv_fill_buffer(cmd_buffer, image->bo,
image->offset + image->dcc_offset,
image->surface.dcc_size, value);

7
src/amd/vulkan/radv_meta_fast_clear.c
View file

@ -706,6 +706,10 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
* FMASK and DCC also imply a fast-clear eliminate.
*/
radv_update_fce_metadata(cmd_buffer, image, false);
/* Mark the image as being decompressed. */
if (decompress_dcc)
radv_update_dcc_metadata(cmd_buffer, image, false);
}
radv_meta_restore(&saved_state, cmd_buffer);
@ -802,6 +806,9 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
radv_unaligned_dispatch(cmd_buffer, image->info.width, image->info.height, 1);
/* Mark this image as actually being decompressed. */
radv_update_dcc_metadata(cmd_buffer, image, false);
/* The fill buffer below does its own saving */
radv_meta_restore(&saved_state, cmd_buffer);

4
src/amd/vulkan/radv_private.h
View file

@ -1206,6 +1206,9 @@ void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, bool value);
void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, bool value);
uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
struct radeon_winsys_bo *bo,
uint64_t offset, uint64_t size, uint32_t value);
@ -1502,6 +1505,7 @@ struct radv_image {
struct radv_cmask_info cmask;
uint64_t clear_value_offset;
uint64_t fce_pred_offset;
uint64_t dcc_pred_offset;
/*
* Metadata for the TC-compat zrange workaround. If the 32-bit value