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i965/compute: Emit GPGPU_WALKER in genX_state_upload
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Jordan Justen
parent
1b85c605a6
commit
c506eae53d
3 changed files with 105 additions and 130 deletions
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@ -34,135 +34,6 @@
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#include "brw_defines.h"
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static void
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prepare_indirect_gpgpu_walker(struct brw_context *brw)
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{
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const struct gen_device_info *devinfo = &brw->screen->devinfo;
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GLintptr indirect_offset = brw->compute.num_work_groups_offset;
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struct brw_bo *bo = brw->compute.num_work_groups_bo;
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brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMX, bo, indirect_offset + 0);
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brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMY, bo, indirect_offset + 4);
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brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMZ, bo, indirect_offset + 8);
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if (devinfo->gen > 7)
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return;
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/* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
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BEGIN_BATCH(7);
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OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2));
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OUT_BATCH(MI_PREDICATE_SRC0 + 4);
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OUT_BATCH(0u);
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OUT_BATCH(MI_PREDICATE_SRC1 + 0);
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OUT_BATCH(0u);
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OUT_BATCH(MI_PREDICATE_SRC1 + 4);
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OUT_BATCH(0u);
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ADVANCE_BATCH();
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/* Load compute_dispatch_indirect_x_size into SRC0 */
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brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 0);
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/* predicate = (compute_dispatch_indirect_x_size == 0); */
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BEGIN_BATCH(1);
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OUT_BATCH(GEN7_MI_PREDICATE |
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MI_PREDICATE_LOADOP_LOAD |
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MI_PREDICATE_COMBINEOP_SET |
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MI_PREDICATE_COMPAREOP_SRCS_EQUAL);
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ADVANCE_BATCH();
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/* Load compute_dispatch_indirect_y_size into SRC0 */
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brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 4);
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/* predicate |= (compute_dispatch_indirect_y_size == 0); */
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BEGIN_BATCH(1);
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OUT_BATCH(GEN7_MI_PREDICATE |
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MI_PREDICATE_LOADOP_LOAD |
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MI_PREDICATE_COMBINEOP_OR |
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MI_PREDICATE_COMPAREOP_SRCS_EQUAL);
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ADVANCE_BATCH();
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/* Load compute_dispatch_indirect_z_size into SRC0 */
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brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 8);
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/* predicate |= (compute_dispatch_indirect_z_size == 0); */
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BEGIN_BATCH(1);
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OUT_BATCH(GEN7_MI_PREDICATE |
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MI_PREDICATE_LOADOP_LOAD |
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MI_PREDICATE_COMBINEOP_OR |
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MI_PREDICATE_COMPAREOP_SRCS_EQUAL);
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ADVANCE_BATCH();
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/* predicate = !predicate; */
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BEGIN_BATCH(1);
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OUT_BATCH(GEN7_MI_PREDICATE |
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MI_PREDICATE_LOADOP_LOADINV |
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MI_PREDICATE_COMBINEOP_OR |
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MI_PREDICATE_COMPAREOP_FALSE);
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ADVANCE_BATCH();
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}
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static void
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brw_emit_gpgpu_walker(struct brw_context *brw)
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{
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const struct gen_device_info *devinfo = &brw->screen->devinfo;
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const struct brw_cs_prog_data *prog_data =
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brw_cs_prog_data(brw->cs.base.prog_data);
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const GLuint *num_groups = brw->compute.num_work_groups;
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uint32_t indirect_flag;
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if (brw->compute.num_work_groups_bo == NULL) {
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indirect_flag = 0;
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} else {
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indirect_flag =
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GEN7_GPGPU_INDIRECT_PARAMETER_ENABLE |
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(devinfo->gen == 7 ? GEN7_GPGPU_PREDICATE_ENABLE : 0);
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prepare_indirect_gpgpu_walker(brw);
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}
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const unsigned simd_size = prog_data->simd_size;
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unsigned group_size = prog_data->local_size[0] *
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prog_data->local_size[1] * prog_data->local_size[2];
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unsigned thread_width_max =
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(group_size + simd_size - 1) / simd_size;
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uint32_t right_mask = 0xffffffffu >> (32 - simd_size);
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const unsigned right_non_aligned = group_size & (simd_size - 1);
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if (right_non_aligned != 0)
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right_mask >>= (simd_size - right_non_aligned);
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uint32_t dwords = devinfo->gen < 8 ? 11 : 15;
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BEGIN_BATCH(dwords);
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OUT_BATCH(GPGPU_WALKER << 16 | (dwords - 2) | indirect_flag);
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OUT_BATCH(0);
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if (devinfo->gen >= 8) {
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OUT_BATCH(0); /* Indirect Data Length */
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OUT_BATCH(0); /* Indirect Data Start Address */
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}
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assert(thread_width_max <= brw->screen->devinfo.max_cs_threads);
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OUT_BATCH(SET_FIELD(simd_size / 16, GPGPU_WALKER_SIMD_SIZE) |
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SET_FIELD(thread_width_max - 1, GPGPU_WALKER_THREAD_WIDTH_MAX));
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OUT_BATCH(0); /* Thread Group ID Starting X */
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if (devinfo->gen >= 8)
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OUT_BATCH(0); /* MBZ */
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OUT_BATCH(num_groups[0]); /* Thread Group ID X Dimension */
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OUT_BATCH(0); /* Thread Group ID Starting Y */
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if (devinfo->gen >= 8)
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OUT_BATCH(0); /* MBZ */
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OUT_BATCH(num_groups[1]); /* Thread Group ID Y Dimension */
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OUT_BATCH(0); /* Thread Group ID Starting/Resume Z */
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OUT_BATCH(num_groups[2]); /* Thread Group ID Z Dimension */
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OUT_BATCH(right_mask); /* Right Execution Mask */
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OUT_BATCH(0xffffffff); /* Bottom Execution Mask */
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ADVANCE_BATCH();
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BEGIN_BATCH(2);
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OUT_BATCH(MEDIA_STATE_FLUSH << 16 | (2 - 2));
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OUT_BATCH(0);
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ADVANCE_BATCH();
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}
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static void
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brw_dispatch_compute_common(struct gl_context *ctx)
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{
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@ -191,7 +62,7 @@ brw_dispatch_compute_common(struct gl_context *ctx)
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brw->batch.no_wrap = true;
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brw_upload_compute_state(brw);
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brw_emit_gpgpu_walker(brw);
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brw->vtbl.emit_compute_walker(brw);
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brw->batch.no_wrap = false;
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@ -752,6 +752,8 @@ struct brw_context
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struct brw_bo *bo,
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uint32_t offset_in_bytes,
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uint32_t report_id);
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void (*emit_compute_walker)(struct brw_context *brw);
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} vtbl;
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struct brw_bufmgr *bufmgr;
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@ -4579,6 +4579,107 @@ static const struct brw_tracked_state genX(cs_state) = {
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.emit = genX(upload_cs_state)
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};
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#define GPGPU_DISPATCHDIMX 0x2500
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#define GPGPU_DISPATCHDIMY 0x2504
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#define GPGPU_DISPATCHDIMZ 0x2508
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#define MI_PREDICATE_SRC0 0x2400
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#define MI_PREDICATE_SRC1 0x2408
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static void
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prepare_indirect_gpgpu_walker(struct brw_context *brw)
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{
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GLintptr indirect_offset = brw->compute.num_work_groups_offset;
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struct brw_bo *bo = brw->compute.num_work_groups_bo;
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emit_lrm(brw, GPGPU_DISPATCHDIMX, ro_bo(bo, indirect_offset + 0));
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emit_lrm(brw, GPGPU_DISPATCHDIMY, ro_bo(bo, indirect_offset + 4));
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emit_lrm(brw, GPGPU_DISPATCHDIMZ, ro_bo(bo, indirect_offset + 8));
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#if GEN_GEN <= 7
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/* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
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emit_lri(brw, MI_PREDICATE_SRC0 + 4, 0);
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emit_lri(brw, MI_PREDICATE_SRC1 , 0);
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emit_lri(brw, MI_PREDICATE_SRC1 + 4, 0);
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/* Load compute_dispatch_indirect_x_size into SRC0 */
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emit_lrm(brw, MI_PREDICATE_SRC0, ro_bo(bo, indirect_offset + 0));
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/* predicate = (compute_dispatch_indirect_x_size == 0); */
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brw_batch_emit(brw, GENX(MI_PREDICATE), mip) {
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mip.LoadOperation = LOAD_LOAD;
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mip.CombineOperation = COMBINE_SET;
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mip.CompareOperation = COMPARE_SRCS_EQUAL;
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}
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/* Load compute_dispatch_indirect_y_size into SRC0 */
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emit_lrm(brw, MI_PREDICATE_SRC0, ro_bo(bo, indirect_offset + 4));
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/* predicate |= (compute_dispatch_indirect_y_size == 0); */
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brw_batch_emit(brw, GENX(MI_PREDICATE), mip) {
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mip.LoadOperation = LOAD_LOAD;
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mip.CombineOperation = COMBINE_OR;
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mip.CompareOperation = COMPARE_SRCS_EQUAL;
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}
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/* Load compute_dispatch_indirect_z_size into SRC0 */
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emit_lrm(brw, MI_PREDICATE_SRC0, ro_bo(bo, indirect_offset + 8));
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/* predicate |= (compute_dispatch_indirect_z_size == 0); */
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brw_batch_emit(brw, GENX(MI_PREDICATE), mip) {
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mip.LoadOperation = LOAD_LOAD;
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mip.CombineOperation = COMBINE_OR;
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mip.CompareOperation = COMPARE_SRCS_EQUAL;
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}
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/* predicate = !predicate; */
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#define COMPARE_FALSE 1
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brw_batch_emit(brw, GENX(MI_PREDICATE), mip) {
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mip.LoadOperation = LOAD_LOADINV;
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mip.CombineOperation = COMBINE_OR;
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mip.CompareOperation = COMPARE_FALSE;
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}
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#endif
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}
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static void
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genX(emit_gpgpu_walker)(struct brw_context *brw)
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{
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const struct brw_cs_prog_data *prog_data =
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brw_cs_prog_data(brw->cs.base.prog_data);
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const GLuint *num_groups = brw->compute.num_work_groups;
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bool indirect = brw->compute.num_work_groups_bo != NULL;
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if (indirect)
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prepare_indirect_gpgpu_walker(brw);
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const unsigned simd_size = prog_data->simd_size;
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unsigned group_size = prog_data->local_size[0] *
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prog_data->local_size[1] * prog_data->local_size[2];
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uint32_t right_mask = 0xffffffffu >> (32 - simd_size);
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const unsigned right_non_aligned = group_size & (simd_size - 1);
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if (right_non_aligned != 0)
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right_mask >>= (simd_size - right_non_aligned);
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brw_batch_emit(brw, GENX(GPGPU_WALKER), ggw) {
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ggw.IndirectParameterEnable = indirect;
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ggw.PredicateEnable = GEN_GEN <= 7 && indirect;
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ggw.SIMDSize = prog_data->simd_size / 16;
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ggw.ThreadDepthCounterMaximum = 0;
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ggw.ThreadHeightCounterMaximum = 0;
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ggw.ThreadWidthCounterMaximum = prog_data->threads - 1;
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ggw.ThreadGroupIDXDimension = num_groups[0];
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ggw.ThreadGroupIDYDimension = num_groups[1];
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ggw.ThreadGroupIDZDimension = num_groups[2];
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ggw.RightExecutionMask = right_mask;
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ggw.BottomExecutionMask = 0xffffffff;
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}
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brw_batch_emit(brw, GENX(MEDIA_STATE_FLUSH), msf);
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}
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#endif
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/* ---------------------------------------------------------------------- */
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@ -5972,5 +6073,6 @@ genX(init_atoms)(struct brw_context *brw)
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compute_atoms, ARRAY_SIZE(compute_atoms));
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brw->vtbl.emit_mi_report_perf_count = genX(emit_mi_report_perf_count);
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brw->vtbl.emit_compute_walker = genX(emit_gpgpu_walker);
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#endif
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}
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