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i965/fs: Handle MRF destinations in lower_integer_multiplication().

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The lowered code reads from the destination, which isn't possible from
message registers.

Fixes the following dEQP tests on SNB:

    dEQP-GLES3.functional.shaders.precision.int.highp_mul_fragment
    dEQP-GLES3.functional.shaders.precision.int.mediump_mul_fragment
    dEQP-GLES3.functional.shaders.precision.int.lowp_mul_fragment

Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Tested-by:  Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
(cherry picked from commit 9390cb8459)
This commit is contained in:
Matt Turner 2015-09-02 12:49:08 -07:00 • committed by Emil Velikov
parent b0bce4c783
commit 34d34076ff
1 changed files with 4 additions and 4 deletions
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8
src/mesa/drivers/dri/i965/brw_fs.cpp
View file

@ -3607,7 +3607,8 @@ fs_visitor::lower_integer_multiplication()
* schedule multi-component multiplications much better.
*/
if (inst->conditional_mod && inst->dst.is_null()) {
fs_reg orig_dst = inst->dst;
if (orig_dst.is_null() || orig_dst.file == MRF) {
inst->dst = fs_reg(GRF, alloc.allocate(dispatch_width / 8),
inst->dst.type, dispatch_width);
}
@ -3673,9 +3674,8 @@ fs_visitor::lower_integer_multiplication()
insert(ADD(dst, low, high));
if (inst->conditional_mod) {
fs_reg null(retype(brw_null_reg(), inst->dst.type));
fs_inst *mov = MOV(null, inst->dst);
if (inst->conditional_mod || orig_dst.file == MRF) {
fs_inst *mov = MOV(orig_dst, inst->dst);
mov->conditional_mod = inst->conditional_mod;
insert(mov);
}