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radeonsi: fix a Unigine Heaven hang when drirc is missing

Browse source 
Cc: 10.6 11.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit 9b510a9652)

Conflicts:
	src/gallium/drivers/radeonsi/si_shader.h
	src/gallium/drivers/radeonsi/si_state_shaders.c
This commit is contained in:
Marek Olšák 2015-08-29 22:59:23 +02:00 • committed by Emil Velikov
parent b2cdcc8b29
commit b0bce4c783
4 changed files with 29 additions and 1 deletions
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1
src/gallium/drivers/radeonsi/si_shader.h
View file

@ -116,6 +116,7 @@ struct si_shader_selector {
unsigned gs_output_prim;
unsigned gs_max_out_vertices;
uint64_t gs_used_inputs; /* mask of "get_unique_index" bits */
uint32_t ps_colors_written;
};
union si_shader_key {

16
src/gallium/drivers/radeonsi/si_state.c
View file

@ -29,6 +29,7 @@
#include "sid.h"
#include "radeon/r600_cs.h"
#include "util/u_dual_blend.h"
#include "util/u_format.h"
#include "util/u_format_s3tc.h"
#include "util/u_memory.h"
@ -218,8 +219,10 @@ static unsigned si_pack_float_12p4(float x)
* - The COLOR1 format isn't INVALID because of possible dual-source blending,
* so COLOR1 is enabled pretty much all the time.
* So CB_TARGET_MASK is the only register that can disable COLOR1.
*
* Another reason is to avoid a hang with dual source blending.
*/
static void si_update_fb_blend_state(struct si_context *sctx)
void si_update_fb_blend_state(struct si_context *sctx)
{
struct si_pm4_state *pm4;
struct si_state_blend *blend = sctx->queued.named.blend;
@ -237,6 +240,16 @@ static void si_update_fb_blend_state(struct si_context *sctx)
mask |= 0xf << (4*i);
mask &= blend->cb_target_mask;
/* Avoid a hang that happens when dual source blending is enabled
* but there is not enough color outputs. This is undefined behavior,
* so disable color writes completely.
*
* Reproducible with Unigine Heaven 4.0 and drirc missing.
*/
if (blend->dual_src_blend &&
(sctx->ps_shader->ps_colors_written & 0x3) != 0x3)
mask = 0;
si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
si_pm4_set_state(sctx, fb_blend, pm4);
}
@ -328,6 +341,7 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
return NULL;
blend->alpha_to_one = state->alpha_to_one;
blend->dual_src_blend = util_blend_state_is_dual(state, 0);
if (state->logicop_enable) {
color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));

2
src/gallium/drivers/radeonsi/si_state.h
View file

@ -39,6 +39,7 @@ struct si_state_blend {
struct si_pm4_state pm4;
uint32_t cb_target_mask;
bool alpha_to_one;
bool dual_src_blend;
};
struct si_state_sample_mask {
@ -247,6 +248,7 @@ void si_shader_change_notify(struct si_context *sctx);
/* si_state.c */
struct si_shader_selector;
void si_update_fb_blend_state(struct si_context *sctx);
boolean si_is_format_supported(struct pipe_screen *screen,
enum pipe_format format,
enum pipe_texture_target target,

11
src/gallium/drivers/radeonsi/si_state_shaders.c
View file

@ -493,6 +493,16 @@ static void *si_create_shader_state(struct pipe_context *ctx,
1llu << si_shader_io_get_unique_index(name, index);
}
}
break;
case PIPE_SHADER_FRAGMENT:
for (i = 0; i < sel->info.num_outputs; i++) {
unsigned name = sel->info.output_semantic_name[i];
unsigned index = sel->info.output_semantic_index[i];
if (name == TGSI_SEMANTIC_COLOR)
sel->ps_colors_written |= 1 << index;
}
break;
}
if (sscreen->b.debug_flags & DBG_PRECOMPILE)
@ -574,6 +584,7 @@ static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
}
sctx->ps_shader = sel;
si_update_fb_blend_state(sctx);
}
static void si_delete_shader_selector(struct pipe_context *ctx,