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aco/ra: allow VCC on SMEM sbase operand on GFX10+

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Totals from 26 (0.02% of 146267) affected shaders (Navi10):
CodeSize: 324764 -> 324560 (-0.06%)
Instrs: 61090 -> 61039 (-0.08%)
Cycles: 2681952 -> 2668872 (-0.49%)
VMEM: 5773 -> 5769 (-0.07%)
SMEM: 1621 -> 1611 (-0.62%)
SClause: 2546 -> 2543 (-0.12%)
Copies: 4671 -> 4620 (-1.09%)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9531>
This commit is contained in:
Daniel Schürmann 2021-03-11 13:45:45 +01:00 • committed by Marge Bot
parent fc3606f29c
commit 3413c48375
1 changed files with 1 additions and 1 deletions
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2
src/amd/compiler/aco_register_allocation.cpp
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@ -1736,7 +1736,7 @@ bool operand_can_use_reg(chip_class chip, aco_ptr<Instruction>& instr, unsigned
return reg != scc &&
reg != exec &&
(reg != m0 || idx == 1 || idx == 3) && /* offset can be m0 */
(reg != vcc || (instr->definitions.empty() && idx == 2)); /* sdata can be vcc */
(reg != vcc || (instr->definitions.empty() && idx == 2) || chip >= GFX10); /* sdata can be vcc */
default:
// TODO: there are more instructions with restrictions on registers
return true;