From 3413c4837522b069702f45f1ea5fc8351adb7137 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20Sch=C3=BCrmann?= Date: Thu, 11 Mar 2021 13:45:45 +0100 Subject: [PATCH] aco/ra: allow VCC on SMEM sbase operand on GFX10+ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Totals from 26 (0.02% of 146267) affected shaders (Navi10): CodeSize: 324764 -> 324560 (-0.06%) Instrs: 61090 -> 61039 (-0.08%) Cycles: 2681952 -> 2668872 (-0.49%) VMEM: 5773 -> 5769 (-0.07%) SMEM: 1621 -> 1611 (-0.62%) SClause: 2546 -> 2543 (-0.12%) Copies: 4671 -> 4620 (-1.09%) Reviewed-by: Timur Kristóf Part-of: --- src/amd/compiler/aco_register_allocation.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp index 756446279e3..ab1a674dd79 100644 --- a/src/amd/compiler/aco_register_allocation.cpp +++ b/src/amd/compiler/aco_register_allocation.cpp @@ -1736,7 +1736,7 @@ bool operand_can_use_reg(chip_class chip, aco_ptr& instr, unsigned return reg != scc && reg != exec && (reg != m0 || idx == 1 || idx == 3) && /* offset can be m0 */ - (reg != vcc || (instr->definitions.empty() && idx == 2)); /* sdata can be vcc */ + (reg != vcc || (instr->definitions.empty() && idx == 2) || chip >= GFX10); /* sdata can be vcc */ default: // TODO: there are more instructions with restrictions on registers return true;