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radeonsi: always lower alu bit sizes

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Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13072

load_vs_input_from_vertex_buffer can create unsupported 16bit shifts on GFX6/7.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34946>
This commit is contained in:
Georg Lehmann 2025-05-11 15:01:05 +02:00 • committed by Marge Bot
parent 804567ddd8
commit 33b5d8b2ec
1 changed files with 6 additions and 7 deletions
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13
src/gallium/drivers/radeonsi/si_shader.c
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@ -2542,16 +2542,15 @@ static void run_late_optimization_and_lowering_passes(struct si_nir_shader_ctx *
NIR_PASS(progress, nir, ac_nir_lower_mem_access_bit_sizes,
sel->screen->info.gfx_level, !nir->info.use_aco_amd);
if (nir->info.stage == MESA_SHADER_KERNEL) {
if (nir->info.stage == MESA_SHADER_KERNEL)
NIR_PASS(progress, nir, ac_nir_lower_global_access);
if (nir->info.bit_sizes_int & (8 | 16)) {
if (sel->screen->info.gfx_level >= GFX8)
nir_divergence_analysis(nir);
if (ac_nir_might_lower_bit_size(nir)) {
if (sel->screen->info.gfx_level >= GFX8)
nir_divergence_analysis(nir);
NIR_PASS(progress, nir, nir_lower_bit_size, ac_nir_lower_bit_size_callback,
&sel->screen->info.gfx_level);
}
NIR_PASS(progress, nir, nir_lower_bit_size, ac_nir_lower_bit_size_callback,
&sel->screen->info.gfx_level);
}
/* This must be after lowering resources to descriptor loads and before lowering intrinsics