From 33b5d8b2ec26904ec1c331dd64ee04e351fd8e0e Mon Sep 17 00:00:00 2001 From: Georg Lehmann Date: Sun, 11 May 2025 15:01:05 +0200 Subject: [PATCH] radeonsi: always lower alu bit sizes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13072 load_vs_input_from_vertex_buffer can create unsupported 16bit shifts on GFX6/7. Reviewed-by: Marek Olšák Reviewed-by: Qiang Yu Cc: mesa-stable Part-of: --- src/gallium/drivers/radeonsi/si_shader.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index eb9b37e3ec0..dfb5f6e3017 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -2542,16 +2542,15 @@ static void run_late_optimization_and_lowering_passes(struct si_nir_shader_ctx * NIR_PASS(progress, nir, ac_nir_lower_mem_access_bit_sizes, sel->screen->info.gfx_level, !nir->info.use_aco_amd); - if (nir->info.stage == MESA_SHADER_KERNEL) { + if (nir->info.stage == MESA_SHADER_KERNEL) NIR_PASS(progress, nir, ac_nir_lower_global_access); - if (nir->info.bit_sizes_int & (8 | 16)) { - if (sel->screen->info.gfx_level >= GFX8) - nir_divergence_analysis(nir); + if (ac_nir_might_lower_bit_size(nir)) { + if (sel->screen->info.gfx_level >= GFX8) + nir_divergence_analysis(nir); - NIR_PASS(progress, nir, nir_lower_bit_size, ac_nir_lower_bit_size_callback, - &sel->screen->info.gfx_level); - } + NIR_PASS(progress, nir, nir_lower_bit_size, ac_nir_lower_bit_size_callback, + &sel->screen->info.gfx_level); } /* This must be after lowering resources to descriptor loads and before lowering intrinsics