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radv: add video decoder register setup.

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This just assigns the correct registers depending on the gpu family.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20388>
This commit is contained in:
Dave Airlie 2022-03-14 11:01:22 +10:00
parent 85eead4198
commit 3253340916
4 changed files with 96 additions and 0 deletions
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1
src/amd/vulkan/meson.build
View file

@ -112,6 +112,7 @@ libradv_files = files(
'radv_spm.c',
'radv_sqtt.c',
'radv_query.c',
'radv_video.c',
'radv_wsi.c',
'si_cmd_buffer.c',
'vk_format.h',

2
src/amd/vulkan/radv_device.c
View file

@ -989,6 +989,8 @@ radv_physical_device_try_create(struct radv_instance *instance, drmDevicePtr drm
/* We don't check the error code, but later check if it is initialized. */
ac_init_perfcounters(&device->rad_info, false, false, &device->ac_perfcounters);
radv_init_physical_device_decoder(device);
/* The WSI is structured as a layer on top of the driver, so this has
* to be the last part of initialization (at least until we get other
* semi-layers).

10
src/amd/vulkan/radv_private.h
View file

@ -348,6 +348,13 @@ struct radv_physical_device {
uint32_t num_perfcounters;
struct radv_perfcounter_desc *perfcounters;
struct {
unsigned data0;
unsigned data1;
unsigned cmd;
unsigned cntl;
} vid_dec_reg;
};
uint32_t radv_find_memory_index(struct radv_physical_device *pdevice, VkMemoryPropertyFlags flags);
@ -3441,6 +3448,9 @@ radv_queue_ring(struct radv_queue *queue)
return radv_queue_family_to_ring(queue->device->physical_device, queue->state.qf);
}
/* radv_video */
void radv_init_physical_device_decoder(struct radv_physical_device *pdevice);
/**
* Helper used for debugging compiler issues by enabling/disabling LLVM for a
* specific shader stage (developers only).

83
src/amd/vulkan/radv_video.c Normal file
View file

@ -0,0 +1,83 @@
/**************************************************************************
*
* Copyright 2017 Advanced Micro Devices, Inc.
* Copyright 2021 Red Hat Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
#include "radv_private.h"
#include "ac_vcn_dec.h"
#include "ac_uvd_dec.h"
void
radv_init_physical_device_decoder(struct radv_physical_device *pdevice)
{
switch (pdevice->rad_info.family) {
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
pdevice->vid_dec_reg.data0 = RUVD_GPCOM_VCPU_DATA0_SOC15;
pdevice->vid_dec_reg.data1 = RUVD_GPCOM_VCPU_DATA1_SOC15;
pdevice->vid_dec_reg.cmd = RUVD_GPCOM_VCPU_CMD_SOC15;
pdevice->vid_dec_reg.cntl = RUVD_ENGINE_CNTL_SOC15;
break;
case CHIP_RAVEN:
case CHIP_RAVEN2:
pdevice->vid_dec_reg.data0 = RDECODE_VCN1_GPCOM_VCPU_DATA0;
pdevice->vid_dec_reg.data1 = RDECODE_VCN1_GPCOM_VCPU_DATA1;
pdevice->vid_dec_reg.cmd = RDECODE_VCN1_GPCOM_VCPU_CMD;
pdevice->vid_dec_reg.cntl = RDECODE_VCN1_ENGINE_CNTL;
break;
case CHIP_NAVI10:
case CHIP_NAVI12:
case CHIP_NAVI14:
case CHIP_RENOIR:
pdevice->vid_dec_reg.data0 = RDECODE_VCN2_GPCOM_VCPU_DATA0;
pdevice->vid_dec_reg.data1 = RDECODE_VCN2_GPCOM_VCPU_DATA1;
pdevice->vid_dec_reg.cmd = RDECODE_VCN2_GPCOM_VCPU_CMD;
pdevice->vid_dec_reg.cntl = RDECODE_VCN2_ENGINE_CNTL;
break;
case CHIP_MI100:
case CHIP_MI200:
case CHIP_NAVI21:
case CHIP_NAVI22:
case CHIP_NAVI23:
case CHIP_NAVI24:
case CHIP_VANGOGH:
case CHIP_REMBRANDT:
pdevice->vid_dec_reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
pdevice->vid_dec_reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
pdevice->vid_dec_reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;
pdevice->vid_dec_reg.cntl = RDECODE_VCN2_5_ENGINE_CNTL;
break;
default:
if (radv_has_uvd(pdevice)) {
pdevice->vid_dec_reg.data0 = RUVD_GPCOM_VCPU_DATA0;
pdevice->vid_dec_reg.data1 = RUVD_GPCOM_VCPU_DATA1;
pdevice->vid_dec_reg.cmd = RUVD_GPCOM_VCPU_CMD;
pdevice->vid_dec_reg.cntl = RUVD_ENGINE_CNTL;
}
break;
}
}