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i965/vec4/gen6: fix exec_size for instructions with width of 4 in generate_gs_svb_write()

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Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Samuel Iglesias Gonsalvez 2015-12-03 18:27:39 +01:00 • committed by Samuel Iglesias Gonsálvez
parent 2fafc6b98c
commit 30fc3fa24d
1 changed files with 3 additions and 0 deletions
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src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
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@ -485,10 +485,13 @@ generate_gs_svb_write(struct brw_codegen *p,
bool final_write = inst->sol_final_write; bool final_write = inst->sol_final_write;
brw_push_insn_state(p); brw_push_insn_state(p);
brw_set_default_exec_size(p, BRW_EXECUTE_4);
/* Copy Vertex data into M0.x */ /* Copy Vertex data into M0.x */
brw_MOV(p, stride(dst, 4, 4, 1), brw_MOV(p, stride(dst, 4, 4, 1),
stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1)); stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
brw_pop_insn_state(p);
brw_push_insn_state(p);
/* Send SVB Write */ /* Send SVB Write */
brw_svb_write(p, brw_svb_write(p,
final_write ? src1 : brw_null_reg(), /* dest == src1 */ final_write ? src1 : brw_null_reg(), /* dest == src1 */