fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-05 04:40:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

iris,anv/xe2+: Enable the DX10/OGL border mode for YCrCb as per Wa_14014226147.

Browse source 
Hardware defaults to DX9 YCrCb border color mode instead of the
behavior expected for DX10/OGL.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29562>
This commit is contained in:
Francisco Jerez 2024-06-17 14:01:54 -07:00
parent c8c9d1a802
commit 2aa4652a68
3 changed files with 37 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
src/gallium/drivers/iris/iris_state.c
View file

@ -1369,6 +1369,13 @@ iris_init_render_context(struct iris_batch *batch)
};
#endif
#if GFX_VER >= 20
iris_emit_cmd(batch, GENX(3DSTATE_3D_MODE), p) {
p.DX10OGLBorderModeforYCRCB = true;
p.DX10OGLBorderModeforYCRCBMask = true;
}
#endif
upload_pixel_hashing_tables(batch);
/* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid

23
src/intel/genxml/gen20.xml
View file

@ -320,6 +320,29 @@
<field name="Constant Cache" start="61" end="61" type="bool" />
<field name="Barrier ID Address" start="67" end="127" type="address" />
</struct>
<instruction name="3DSTATE_3D_MODE" bias="2" length="5" engine="render">
<field name="DWord Length" start="0" end="7" type="uint" default="3" />
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="30" />
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1" />
<field name="Command SubType" start="27" end="28" type="uint" default="3" />
<field name="Command Type" start="29" end="31" type="uint" default="3" />
<field name="Cross Slice Hashing Mode" start="32" end="33" type="uint">
<value name="Normal Mode" value="0" />
<value name="Disable" value="1" />
<value name="hashing 32x32" value="3" />
</field>
<field name="3D Scoreboard Hashing Mode" start="36" end="36" type="bool" />
<field name="Subslice Hashing Table Enable" start="37" end="37" type="bool" />
<field name="Slice Hashing Table Enable" start="38" end="38" type="bool" />
<field name="DX10 OGL Border Mode for YCRCB" start="42" end="42" type="bool" />
<field name="Cross Slice Hashing Mode Mask" start="48" end="49" type="int" />
<field name="3D Scoreboard Hashing Mode Mask" start="52" end="52" type="bool" />
<field name="Subslice Hashing Table Enable Mask" start="53" end="53" type="bool" />
<field name="Slice Hashing Table Enable Mask" start="54" end="54" type="bool" />
<field name="DX10 OGL Border Mode for YCRCB Mask" start="58" end="58" type="bool" />
<field name="RCC RHWO Optimization Disable" start="111" end="111" type="bool" />
<field name="RCC RHWO Optimization Disable Mask" start="127" end="127" type="bool" />
</instruction>
<instruction name="3DSTATE_BTD" bias="2" length="6" engine="render|compute">
<field name="DWord Length" start="0" end="7" type="uint" default="4" />
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="6" />

7
src/intel/vulkan/genX_init_state.c
View file

@ -628,6 +628,13 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch)
genX(emit_pipeline_select)(batch, _3D, device);
#endif
#if GFX_VER >= 20
anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), p) {
p.DX10OGLBorderModeforYCRCB = true;
p.DX10OGLBorderModeforYCRCBMask = true;
}
#endif
anv_batch_emit(batch, GENX(MI_BATCH_BUFFER_END), bbe);
result = batch->status;