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radeonsi: Reinitialize all descriptors in CE preamble.

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This fixes a problem with the CE preamble and restoring only stuff in the
preamble when needed.

To illustrate suppose we have two graphics IB's 1 and 2, which  are submitted in
that order. Furthermore suppose IB 1 does not use CE ram, but IB 2 does, and we
have a context switch at the start of IB 1, but not between IB 1 and IB 2.

The old code put the CE RAM loads in the preamble of IB 2. As the preamble of
IB 1 does not have the loads and the preamble of IB 2 does not get executed, the
old values are not load into CE RAM.

Fix this by always restoring the entire CE RAM.

v2: - Just load all descriptor set buffers instead of load and store the entire
      CE RAM.
    - Leave the ce_ram_dirty tracking in place for the non-preamble case.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

Note: This commit differs from the one in master - 54f755fa0f
("radeonsi: Reinitialize all descriptors in CE preamble.")
This commit is contained in:
Bas Nieuwenhuizen 2016-06-06 22:49:57 +02:00 • committed by Emil Velikov
parent 7bed792ebb
commit 28294573c7
3 changed files with 17 additions and 2 deletions
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15
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -159,7 +159,7 @@ static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned s
return true;
}
static void si_reinitialize_ce_ram(struct si_context *sctx,
static void si_ce_reinitialize_descriptors(struct si_context *sctx,
struct si_descriptors *desc)
{
if (desc->buffer) {
@ -185,6 +185,17 @@ static void si_reinitialize_ce_ram(struct si_context *sctx,
desc->ce_ram_dirty = false;
}
void si_ce_reinitialize_all_descriptors(struct si_context *sctx)
{
for (int i = 0; i < SI_NUM_SHADERS; i++) {
si_ce_reinitialize_descriptors(sctx, &sctx->const_buffers[i].desc);
si_ce_reinitialize_descriptors(sctx, &sctx->shader_buffers[i].desc);
si_ce_reinitialize_descriptors(sctx, &sctx->samplers[i].views.desc);
si_ce_reinitialize_descriptors(sctx, &sctx->images[i].desc);
}
si_ce_reinitialize_descriptors(sctx, &sctx->rw_buffers.desc);
}
void si_ce_enable_loads(struct radeon_winsys_cs *ib)
{
radeon_emit(ib, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
@ -206,7 +217,7 @@ static bool si_upload_descriptors(struct si_context *sctx,
uint32_t const* list = (uint32_t const*)desc->list;
if (desc->ce_ram_dirty)
si_reinitialize_ce_ram(sctx, desc);
si_ce_reinitialize_descriptors(sctx, desc);
while(desc->dirty_mask) {
int begin, count;

3
src/gallium/drivers/radeonsi/si_hw_context.c
View file

@ -207,6 +207,9 @@ void si_begin_new_cs(struct si_context *ctx)
else if (ctx->ce_ib)
si_ce_enable_loads(ctx->ce_ib);
if (ctx->ce_preamble_ib)
si_ce_reinitialize_all_descriptors(ctx);
ctx->framebuffer.dirty_cbufs = (1 << 8) - 1;
ctx->framebuffer.dirty_zsbuf = true;
si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);

1
src/gallium/drivers/radeonsi/si_state.h
View file

@ -250,6 +250,7 @@ struct si_buffer_resources {
} while(0)
/* si_descriptors.c */
void si_ce_reinitialize_all_descriptors(struct si_context *sctx);
void si_ce_enable_loads(struct radeon_winsys_cs *ib);
void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
struct pipe_resource *buffer,