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radeonsi: Reinitialize all descriptors in CE preamble.

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This fixes a problem with the CE preamble and restoring only stuff in the
preamble when needed.

To illustrate suppose we have two graphics IB's 1 and 2, which  are submitted in
that order. Furthermore suppose IB 1 does not use CE ram, but IB 2 does, and we
have a context switch at the start of IB 1, but not between IB 1 and IB 2.

The old code put the CE RAM loads in the preamble of IB 2. As the preamble of
IB 1 does not have the loads and the preamble of IB 2 does not get executed, the
old values are not load into CE RAM.

Fix this by always restoring the entire CE RAM.

v2: - Just load all descriptor set buffers instead of load and store the entire
      CE RAM.
    - Leave the ce_ram_dirty tracking in place for the non-preamble case.

v3: - Fixed parameter alignment.
    - Rebased to master (Nicolai's descriptor series).

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Bas Nieuwenhuizen 2016-06-06 22:36:35 +02:00
parent f93c22109e
commit 54f755fa0f
3 changed files with 15 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -160,8 +160,8 @@ static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned s
return true;
}
static void si_reinitialize_ce_ram(struct si_context *sctx,
struct si_descriptors *desc)
static void si_ce_reinitialize_descriptors(struct si_context *sctx,
struct si_descriptors *desc)
{
if (desc->buffer) {
struct r600_resource *buffer = (struct r600_resource*)desc->buffer;
@ -186,6 +186,14 @@ static void si_reinitialize_ce_ram(struct si_context *sctx,
desc->ce_ram_dirty = false;
}
void si_ce_reinitialize_all_descriptors(struct si_context *sctx)
{
int i;
for (i = 0; i < SI_NUM_DESCS; ++i)
si_ce_reinitialize_descriptors(sctx, &sctx->descriptors[i]);
}
void si_ce_enable_loads(struct radeon_winsys_cs *ib)
{
radeon_emit(ib, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
@ -207,7 +215,7 @@ static bool si_upload_descriptors(struct si_context *sctx,
uint32_t const* list = (uint32_t const*)desc->list;
if (desc->ce_ram_dirty)
si_reinitialize_ce_ram(sctx, desc);
si_ce_reinitialize_descriptors(sctx, desc);
while(desc->dirty_mask) {
int begin, count;

3
src/gallium/drivers/radeonsi/si_hw_context.c
View file

@ -213,6 +213,9 @@ void si_begin_new_cs(struct si_context *ctx)
else if (ctx->ce_ib)
si_ce_enable_loads(ctx->ce_ib);
if (ctx->ce_preamble_ib)
si_ce_reinitialize_all_descriptors(ctx);
ctx->framebuffer.dirty_cbufs = (1 << 8) - 1;
ctx->framebuffer.dirty_zsbuf = true;
si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);

1
src/gallium/drivers/radeonsi/si_state.h
View file

@ -276,6 +276,7 @@ struct si_buffer_resources {
} while(0)
/* si_descriptors.c */
void si_ce_reinitialize_all_descriptors(struct si_context *sctx);
void si_ce_enable_loads(struct radeon_winsys_cs *ib);
void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
const struct radeon_surf_level *base_level_info,