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nir: intel/brw: Change the order of sources for nir_dpas_intel
It was by pure luck that all sources (and the result) of nir_dpas_intel had the same number of components. It is possible to support matrix sizes where the accumlator matrix and the result matrix are larger (e.g., 16x8 * 8x16 = 16x16). This breaks all of the assumptions of NIR's infrastructure for code generating intrinsics. Fix the by making the accumulator matrix be the first source. The accumulator and the result will always have the same dimensions (due to rules of matrix multiplication) and the same type (due to restructions of the cooperative matrix extension). This forces them to have the same number of components. This doesn't fix all the potential problems. NIR expects that all 0-sized sources will have the same number of components. This just ensures that the result has the correct number of components. Fixes:6b14da33ad("intel/fs: nir: Add nir_intrinsic_dpas_intel") Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28404> (cherry picked from commita8115221e5)
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4 changed files with 18 additions and 14 deletions
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@ -1674,7 +1674,7 @@
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"description": "nir: intel/brw: Change the order of sources for nir_dpas_intel",
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"nominated": true,
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"nomination_type": 1,
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"resolution": 0,
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"resolution": 1,
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"main_sha": null,
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"because_sha": "6b14da33ad3aa8a30ed5e479eace8bc6470095a7",
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"notes": null
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@ -2025,11 +2025,15 @@ system_value("leaf_procedural_intel", 1, bit_sizes=[1])
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system_value("btd_shader_type_intel", 1)
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system_value("ray_query_global_intel", 1, bit_sizes=[64])
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# Source 0: A matrix (type specified by SRC_TYPE)
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# Source 1: B matrix (type specified by SRC_TYPE)
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# Source 2: Accumulator matrix (type specified by DEST_TYPE)
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# Source 0: Accumulator matrix (type specified by DEST_TYPE)
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# Source 1: A matrix (type specified by SRC_TYPE)
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# Source 2: B matrix (type specified by SRC_TYPE)
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#
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# The matrix parameters are the slices owned by the invocation.
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#
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# The accumulator is source 0 because that is the source the intrinsic
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# infrastructure in NIR uses to determine the number of components in the
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# result.
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intrinsic("dpas_intel", dest_comp=0, src_comp=[0, 0, 0],
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indices=[DEST_TYPE, SRC_TYPE, SATURATE, CMAT_SIGNED_MASK, SYSTOLIC_DEPTH, REPEAT_COUNT],
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flags=[CAN_ELIMINATE])
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@ -4608,7 +4608,7 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb,
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brw_type_for_nir_type(devinfo, nir_intrinsic_src_type(instr));
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dest = retype(dest, dest_type);
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fs_reg src2 = retype(get_nir_src(ntb, instr->src[2]), dest_type);
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fs_reg src0 = retype(get_nir_src(ntb, instr->src[0]), dest_type);
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const fs_reg dest_hf = dest;
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fs_builder bld8 = bld.exec_all().group(8, 0);
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@ -4624,24 +4624,24 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb,
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!s.compiler->lower_dpas) {
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dest = bld8.vgrf(BRW_REGISTER_TYPE_F, rcount);
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if (src2.file != ARF) {
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const fs_reg src2_hf = src2;
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if (src0.file != ARF) {
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const fs_reg src0_hf = src0;
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src2 = bld8.vgrf(BRW_REGISTER_TYPE_F, rcount);
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src0 = bld8.vgrf(BRW_REGISTER_TYPE_F, rcount);
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for (unsigned i = 0; i < 4; i++) {
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bld16.MOV(byte_offset(src2, REG_SIZE * i * 2),
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byte_offset(src2_hf, REG_SIZE * i));
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bld16.MOV(byte_offset(src0, REG_SIZE * i * 2),
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byte_offset(src0_hf, REG_SIZE * i));
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}
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} else {
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src2 = retype(src2, BRW_REGISTER_TYPE_F);
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src0 = retype(src0, BRW_REGISTER_TYPE_F);
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}
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}
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bld8.DPAS(dest,
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src2,
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src0,
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retype(get_nir_src(ntb, instr->src[2]), src_type),
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retype(get_nir_src(ntb, instr->src[1]), src_type),
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retype(get_nir_src(ntb, instr->src[0]), src_type),
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sdepth,
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rcount)
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->saturate = nir_intrinsic_saturate(instr);
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@ -649,9 +649,9 @@ lower_cmat_instr(nir_builder *b, nir_instr *instr, void *_state)
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nir_def *result =
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nir_dpas_intel(b,
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packing_factor * glsl_base_type_get_bit_size(dst_desc.element_type),
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nir_load_deref(b, accum_slice),
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nir_load_deref(b, A_slice),
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nir_load_deref(b, B_slice),
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nir_load_deref(b, accum_slice),
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.dest_type = nir_get_nir_type_for_glsl_base_type(dst_desc.element_type),
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.src_type = nir_get_nir_type_for_glsl_base_type(src_desc.element_type),
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.saturate = nir_intrinsic_saturate(intrin),
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