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intel/brw: Use enums for DPAS source regioning

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Was previously passing 1, 1, 0 as the regioning. This generated
incorrect disassembly because the encoding for a width of 1 is 0. Use
the enums to ensure the correct values are used.

Fixes: 1c92dad5cb ("intel/disasm: Disassembly support for DPAS")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28404>
(cherry picked from commit c6bd6f2a41)
This commit is contained in:
Ian Romanick 2024-03-25 12:52:46 -07:00 • committed by Eric Engestrom
parent b10ce2157b
commit da2e83a332
2 changed files with 13 additions and 4 deletions
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2
.pick_status.json
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@ -1684,7 +1684,7 @@
"description": "intel/brw: Use enums for DPAS source regioning",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "1c92dad5cb7f5d46dfaf56d2f9ce0203c2fbefbe",
"notes": null

15
src/intel/compiler/brw_disasm.c
View file

@ -1560,7 +1560,10 @@ src0_dpas_3src(FILE *file, const struct intel_device_info *devinfo,
if (subreg_nr)
format(file, ".%d", subreg_nr);
src_align1_region(file, 1, 1, 0);
src_align1_region(file,
BRW_VERTICAL_STRIDE_1,
BRW_WIDTH_1,
BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0);
string(file, brw_reg_type_to_letters(type));
@ -1581,7 +1584,10 @@ src1_dpas_3src(FILE *file, const struct intel_device_info *devinfo,
if (subreg_nr)
format(file, ".%d", subreg_nr);
src_align1_region(file, 1, 1, 0);
src_align1_region(file,
BRW_VERTICAL_STRIDE_1,
BRW_WIDTH_1,
BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0);
string(file, brw_reg_type_to_letters(type));
@ -1602,7 +1608,10 @@ src2_dpas_3src(FILE *file, const struct intel_device_info *devinfo,
if (subreg_nr)
format(file, ".%d", subreg_nr);
src_align1_region(file, 1, 1, 0);
src_align1_region(file,
BRW_VERTICAL_STRIDE_1,
BRW_WIDTH_1,
BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0);
string(file, brw_reg_type_to_letters(type));