diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 7e71f87634f..a4ba103c91e 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -679,7 +679,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
     * with LLVM, which only supports RTNE, or RT, where the mode needs to match
     * across separately compiled stages.
     */
-   if (!radv_use_llvm_for_stage(pdev, stage->stage) && !gl_shader_stage_is_rt(stage->stage))
+   if (!radv_use_llvm_for_stage(pdev, stage->stage) && !mesa_shader_stage_is_rt(stage->stage))
       NIR_PASS(_, stage->nir, ac_nir_opt_pack_half, gfx_level);
 
    NIR_PASS(_, stage->nir, nir_lower_load_const_to_scalar);
diff --git a/src/amd/vulkan/radv_pipeline_cache.c b/src/amd/vulkan/radv_pipeline_cache.c
index 0483936279e..9d811480541 100644
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -653,7 +653,7 @@ radv_pipeline_cache_get_binaries(struct radv_device *device, const VkAllocationC
    bool complete = true;
    bool is_rt = false;
    for (unsigned i = 0; i < pipeline_obj->num_shaders; i++) {
-      if (gl_shader_stage_is_rt(pipeline_obj->shaders[i]->info.stage)) {
+      if (mesa_shader_stage_is_rt(pipeline_obj->shaders[i]->info.stage)) {
          is_rt = true;
          break;
       }
diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c
index 842a501e21f..27dfbdb508f 100644
--- a/src/amd/vulkan/radv_shader_args.c
+++ b/src/amd/vulkan/radv_shader_args.c
@@ -554,7 +554,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_graphics
 
    radv_init_shader_args(device, stage, args);
 
-   if (gl_shader_stage_is_rt(stage)) {
+   if (mesa_shader_stage_is_rt(stage)) {
       radv_declare_rt_shader_args(gfx_level, args);
       return;
    }
@@ -883,7 +883,7 @@ radv_declare_shader_args(const struct radv_device *device, const struct radv_gra
 {
    declare_shader_args(device, gfx_state, info, stage, previous_stage, args, NULL);
 
-   if (gl_shader_stage_is_rt(stage))
+   if (mesa_shader_stage_is_rt(stage))
       return;
 
    uint32_t num_user_sgprs = args->num_user_sgprs;
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index ed589a7495a..21f4b716791 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -485,7 +485,7 @@ radv_get_wave_size(struct radv_device *device, mesa_shader_stage stage, const st
       return info->wave_size;
    else if (stage == MESA_SHADER_FRAGMENT)
       return pdev->ps_wave_size;
-   else if (gl_shader_stage_is_rt(stage))
+   else if (mesa_shader_stage_is_rt(stage))
       return pdev->rt_wave_size;
    else
       return pdev->ge_wave_size;
@@ -1174,7 +1174,7 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n
       gather_shader_info_mesh(device, nir, stage_key, info);
       break;
    default:
-      if (gl_shader_stage_is_rt(nir->info.stage))
+      if (mesa_shader_stage_is_rt(nir->info.stage))
          gather_shader_info_rt(nir, info);
       break;
    }
diff --git a/src/compiler/shader_enums.h b/src/compiler/shader_enums.h
index 8b6218e85f2..41be0688550 100644
--- a/src/compiler/shader_enums.h
+++ b/src/compiler/shader_enums.h
@@ -116,7 +116,7 @@ mesa_shader_stage_is_callable(mesa_shader_stage stage)
 }
 
 static inline bool
-gl_shader_stage_is_rt(mesa_shader_stage stage)
+mesa_shader_stage_is_rt(mesa_shader_stage stage)
 {
    return stage == MESA_SHADER_RAYGEN || mesa_shader_stage_is_callable(stage);
 }
diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c
index 57b9ce4009d..649cf5c7705 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -7353,7 +7353,7 @@ spirv_to_nir(const uint32_t *words, size_t word_count,
     * https://gitlab.freedesktop.org/mesa/mesa/-/issues/5326
     * https://gitlab.freedesktop.org/mesa/mesa/-/issues/11585
     */
-   if (gl_shader_stage_is_rt(b->shader->info.stage)) {
+   if (mesa_shader_stage_is_rt(b->shader->info.stage)) {
       NIR_PASS(_, b->shader, nir_remove_dead_variables, nir_var_shader_call_data,
                NULL);
    }
diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp
index 963f0230fa7..17f516bf937 100644
--- a/src/intel/compiler/brw_lower_logical_sends.cpp
+++ b/src/intel/compiler/brw_lower_logical_sends.cpp
@@ -1636,7 +1636,7 @@ lower_lsc_memory_logical_send(const brw_builder &bld, brw_inst *inst)
    /* Disable LSC data port L1 cache scheme for the TGM load/store for RT
     * shaders. (see HSD 18038444588)
     */
-   if (devinfo->ver >= 20 && gl_shader_stage_is_rt(bld.shader->stage) &&
+   if (devinfo->ver >= 20 && mesa_shader_stage_is_rt(bld.shader->stage) &&
        inst->sfid == BRW_SFID_TGM &&
        !lsc_opcode_is_atomic(op)) {
       if (lsc_opcode_is_store(op)) {
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index 0268dc1b432..09c4c88db0a 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -665,7 +665,7 @@ brw_shader::assign_curb_setup()
 
    if (pull_constants) {
       const bool pull_constants_a64 =
-         (gl_shader_stage_is_rt(stage) &&
+         (mesa_shader_stage_is_rt(stage) &&
           brw_bs_prog_data(prog_data)->uses_inline_push_addr) ||
          ((mesa_shader_stage_is_compute(stage) ||
            mesa_shader_stage_is_mesh(stage)) &&
@@ -679,7 +679,7 @@ brw_shader::assign_curb_setup()
           * parameter.
           */
          base_addr =
-            gl_shader_stage_is_rt(stage) ?
+            mesa_shader_stage_is_rt(stage) ?
             retype(bs_payload().inline_parameter, BRW_TYPE_UQ) :
             retype(cs_payload().inline_parameter, BRW_TYPE_UQ);
       } else {