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nvc0/ir: per-patch vars are in a separate address space

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There's no need to attempt to avoid overlapping generic i/o with patch
i/o. By the same token, we can't merge patch and non-patch loads/stores.

This fixes at least the

  tes-both-input-array-*-index-rd

tessellation variable-indexing tests.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
Ilia Mirkin 2015-07-24 00:21:28 -04:00
parent 9d60793a03
commit 24a7d4e437
2 changed files with 9 additions and 11 deletions
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2
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
View file

@ -2085,6 +2085,8 @@ MemoryOpt::runOpt(BasicBlock *bb)
}
if (ldst->getPredicate()) // TODO: handle predicated ld/st
continue;
if (ldst->perPatch) // TODO: create separate per-patch lists
continue;
if (isLoad) {
DataFile file = ldst->src(0).getFile();

18
src/gallium/drivers/nouveau/nvc0/nvc0_program.c
View file

@ -31,7 +31,7 @@
* 124 scalar varying values.
*/
static uint32_t
nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
nvc0_shader_input_address(unsigned sn, unsigned si)
{
switch (sn) {
case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
@ -42,7 +42,7 @@ nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
case TGSI_SEMANTIC_PSIZE: return 0x06c;
case TGSI_SEMANTIC_POSITION: return 0x070;
case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
case TGSI_SEMANTIC_GENERIC: return 0x080 + si * 0x10;
case TGSI_SEMANTIC_FOG: return 0x2e8;
case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
@ -61,7 +61,7 @@ nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
}
static uint32_t
nvc0_shader_output_address(unsigned sn, unsigned si, unsigned ubase)
nvc0_shader_output_address(unsigned sn, unsigned si)
{
switch (sn) {
case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
@ -72,7 +72,7 @@ nvc0_shader_output_address(unsigned sn, unsigned si, unsigned ubase)
case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
case TGSI_SEMANTIC_PSIZE: return 0x06c;
case TGSI_SEMANTIC_POSITION: return 0x070;
case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
case TGSI_SEMANTIC_GENERIC: return 0x080 + si * 0x10;
case TGSI_SEMANTIC_FOG: return 0x2e8;
case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
@ -97,7 +97,7 @@ nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
case TGSI_SEMANTIC_VERTEXID:
info->in[i].mask = 0x1;
info->in[i].slot[0] =
nvc0_shader_input_address(info->in[i].sn, 0, 0) / 4;
nvc0_shader_input_address(info->in[i].sn, 0) / 4;
continue;
default:
break;
@ -113,13 +113,11 @@ nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
static int
nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
{
unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
unsigned offset;
unsigned i, c;
for (i = 0; i < info->numInputs; ++i) {
offset = nvc0_shader_input_address(info->in[i].sn,
info->in[i].si, ubase);
offset = nvc0_shader_input_address(info->in[i].sn, info->in[i].si);
for (c = 0; c < 4; ++c)
info->in[i].slot[c] = (offset + c * 0x4) / 4;
@ -154,13 +152,11 @@ nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
static int
nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
{
unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
unsigned offset;
unsigned i, c;
for (i = 0; i < info->numOutputs; ++i) {
offset = nvc0_shader_output_address(info->out[i].sn,
info->out[i].si, ubase);
offset = nvc0_shader_output_address(info->out[i].sn, info->out[i].si);
for (c = 0; c < 4; ++c)
info->out[i].slot[c] = (offset + c * 0x4) / 4;