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nvc0/ir: kepler can't do indirect shader input/output loads directly
There's a special AL2P instruction (called AFETCH in nv50 ir) which computes a "physical" value to be used with indirect addressing with ALD. Fixes tcs-input-array-*-index-rd tcs-output-array-*-index-wr varying-indexing tessellation tests on Kepler. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
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Ilia Mirkin
parent
22c9339abf
commit
9d60793a03
8 changed files with 75 additions and 6 deletions
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@ -106,6 +106,7 @@ enum operation
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OP_MEMBAR, // memory barrier (mfence, lfence, sfence)
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OP_VFETCH, // indirection 0 in attribute space, indirection 1 is vertex base
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OP_PFETCH, // fetch base address of vertex src0 (immediate) [+ src1]
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OP_AFETCH, // fetch base address of shader input (a[%r1+0x10])
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OP_EXPORT,
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OP_LINTERP,
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OP_PINTERP,
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@ -77,6 +77,7 @@ private:
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void emitMOV(const Instruction *);
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void emitINTERP(const Instruction *);
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void emitAFETCH(const Instruction *);
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void emitPFETCH(const Instruction *);
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void emitVFETCH(const Instruction *);
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void emitEXPORT(const Instruction *);
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@ -1338,6 +1339,23 @@ CodeEmitterGK110::emitFlow(const Instruction *i)
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}
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}
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void
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CodeEmitterGK110::emitAFETCH(const Instruction *i)
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{
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uint32_t offset = i->src(0).get()->reg.data.offset & 0x7ff;
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code[0] = 0x00000002 | (offset << 23);
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code[1] = 0x7d000000 | (offset >> 9);
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if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
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code[1] |= 0x8;
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emitPredicate(i);
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defId(i->def(0), 2);
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srcId(i->src(0).getIndirect(0), 10);
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}
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void
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CodeEmitterGK110::emitPFETCH(const Instruction *i)
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{
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@ -1707,6 +1725,9 @@ CodeEmitterGK110::emitInstruction(Instruction *insn)
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case OP_EXPORT:
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emitEXPORT(insn);
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break;
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case OP_AFETCH:
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emitAFETCH(insn);
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break;
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case OP_PFETCH:
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emitPFETCH(insn);
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break;
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@ -174,6 +174,7 @@ private:
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void emitALD();
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void emitAST();
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void emitISBERD();
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void emitAL2P();
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void emitIPA();
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void emitPIXLD();
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@ -2203,6 +2204,17 @@ CodeEmitterGM107::emitISBERD()
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emitGPR (0x00, insn->def(0));
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}
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void
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CodeEmitterGM107::emitAL2P()
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{
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emitInsn (0xefa00000);
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emitField(0x2f, 2, (insn->getDef(0)->reg.size / 4) - 1);
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emitO (0x20);
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emitField(0x14, 11, insn->src(0).get()->reg.data.offset);
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emitGPR (0x08, insn->src(0).getIndirect(0));
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emitGPR (0x00, insn->def(0));
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}
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void
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CodeEmitterGM107::emitIPA()
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{
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@ -2759,6 +2771,9 @@ CodeEmitterGM107::emitInstruction(Instruction *i)
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case OP_PFETCH:
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emitISBERD();
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break;
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case OP_AFETCH:
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emitAL2P();
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break;
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case OP_LINTERP:
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case OP_PINTERP:
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emitIPA();
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@ -85,6 +85,7 @@ private:
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void emitCCTL(const Instruction *);
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void emitINTERP(const Instruction *);
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void emitAFETCH(const Instruction *);
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void emitPFETCH(const Instruction *);
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void emitVFETCH(const Instruction *);
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void emitEXPORT(const Instruction *);
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@ -1493,6 +1494,21 @@ CodeEmitterNVC0::emitBAR(const Instruction *i)
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}
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}
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void
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CodeEmitterNVC0::emitAFETCH(const Instruction *i)
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{
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code[0] = 0x00000006;
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code[1] = 0x0c000000 | (i->src(0).get()->reg.data.offset & 0x7ff);
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if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
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code[0] |= 0x200;
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emitPredicate(i);
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defId(i->def(0), 14);
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srcId(i->src(0).getIndirect(0), 20);
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}
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void
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CodeEmitterNVC0::emitPFETCH(const Instruction *i)
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{
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@ -1749,6 +1749,7 @@ NVC0LoweringPass::checkPredicate(Instruction *insn)
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bool
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NVC0LoweringPass::visit(Instruction *i)
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{
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bool ret = true;
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bld.setPosition(i, false);
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if (i->cc != CC_ALWAYS)
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@ -1780,7 +1781,8 @@ NVC0LoweringPass::visit(Instruction *i)
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case OP_SQRT:
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return handleSQRT(i);
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case OP_EXPORT:
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return handleEXPORT(i);
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ret = handleEXPORT(i);
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break;
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case OP_EMIT:
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case OP_RESTART:
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return handleOUT(i);
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@ -1843,7 +1845,20 @@ NVC0LoweringPass::visit(Instruction *i)
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default:
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break;
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}
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return true;
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/* Kepler+ has a special opcode to compute a new base address to be used
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* for indirect loads.
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*/
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if (targ->getChipset() >= NVISA_GK104_CHIPSET && !i->perPatch &&
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(i->op == OP_VFETCH || i->op == OP_EXPORT) && i->src(0).isIndirect(0)) {
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Instruction *afetch = bld.mkOp1(OP_AFETCH, TYPE_U32, bld.getSSA(),
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cloneShallow(func, i->getSrc(0)));
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afetch->setIndirect(0, 0, i->getIndirect(0, 0));
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i->src(0).get()->reg.data.offset = 0;
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i->setIndirect(0, 0, afetch->getDef(0));
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}
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return ret;
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}
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bool
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@ -135,6 +135,7 @@ const char *operationStr[OP_LAST + 1] =
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"membar",
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"vfetch",
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"pfetch",
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"afetch",
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"export",
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"linterp",
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"pinterp",
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@ -41,7 +41,7 @@ const uint8_t Target::operationSrcNr[] =
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0, 0, 0, 0, 0, // BRA, CALL, RET, CONT, BREAK,
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0, 0, 0, // PRERET,CONT,BREAK
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0, 0, 0, 0, 0, 0, // BRKPT, JOINAT, JOIN, DISCARD, EXIT, MEMBAR
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1, 1, 2, 1, 2, // VFETCH, PFETCH, EXPORT, LINTERP, PINTERP
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1, 1, 1, 2, 1, 2, // VFETCH, PFETCH, AFETCH, EXPORT, LINTERP, PINTERP
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1, 1, // EMIT, RESTART
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1, 1, 1, // TEX, TXB, TXL,
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1, 1, 1, 1, 1, 1, 2, // TXF, TXQ, TXD, TXG, TXLQ, TEXCSAA, TEXPREP
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@ -96,8 +96,8 @@ const OpClass Target::operationClass[] =
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OPCLASS_FLOW, OPCLASS_FLOW,
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// MEMBAR
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OPCLASS_CONTROL,
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// VFETCH, PFETCH, EXPORT
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OPCLASS_LOAD, OPCLASS_OTHER, OPCLASS_STORE,
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// VFETCH, PFETCH, AFETCH, EXPORT
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OPCLASS_LOAD, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_STORE,
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// LINTERP, PINTERP
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OPCLASS_SFU, OPCLASS_SFU,
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// EMIT, RESTART
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@ -118,7 +118,7 @@ void TargetNV50::initOpInfo()
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static const uint32_t shortForm[(OP_LAST + 31) / 32] =
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{
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// MOV,ADD,SUB,MUL,MAD,SAD,L/PINTERP,RCP,TEX,TXF
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0x00014e40, 0x00000040, 0x00000498, 0x00000000
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0x00014e40, 0x00000040, 0x00000930, 0x00000000
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};
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static const operation noDestList[] =
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{
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