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intel/eu/xe2+: Add definition for size of GRF space on Xe2.

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And use it in various places in the compiler that require knowledge
about the size of the register file.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25514>
This commit is contained in:
Francisco Jerez 2022-07-07 01:15:14 -07:00
parent ff3814abdd
commit 23e14a6c27
4 changed files with 12 additions and 11 deletions
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14
src/intel/compiler/brw_eu_emit.c
View file

@ -93,7 +93,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
if (dest.file == BRW_MESSAGE_REGISTER_FILE)
assert((dest.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver));
else if (dest.file == BRW_GENERAL_REGISTER_FILE)
assert(dest.nr < 128);
assert(dest.nr < XE2_MAX_GRF);
/* The hardware has a restriction where a destination of size Byte with
* a stride of 1 is only allowed for a packed byte MOV. For any other
@ -213,7 +213,7 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
if (reg.file == BRW_MESSAGE_REGISTER_FILE)
assert((reg.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver));
else if (reg.file == BRW_GENERAL_REGISTER_FILE)
assert(reg.nr < 128);
assert(reg.nr < XE2_MAX_GRF);
gfx7_convert_mrf_to_grf(p, &reg);
@ -347,7 +347,7 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
const struct intel_device_info *devinfo = p->devinfo;
if (reg.file == BRW_GENERAL_REGISTER_FILE)
assert(reg.nr < 128);
assert(reg.nr < XE2_MAX_GRF);
if (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDS ||
brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDSC ||
@ -811,15 +811,15 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
gfx7_convert_mrf_to_grf(p, &dest);
assert(dest.nr < 128);
assert(dest.nr < XE2_MAX_GRF);
if (devinfo->ver >= 10)
assert(!(src0.file == BRW_IMMEDIATE_VALUE &&
src2.file == BRW_IMMEDIATE_VALUE));
assert(src0.file == BRW_IMMEDIATE_VALUE || src0.nr < 128);
assert(src1.file != BRW_IMMEDIATE_VALUE && src1.nr < 128);
assert(src2.file == BRW_IMMEDIATE_VALUE || src2.nr < 128);
assert(src0.file == BRW_IMMEDIATE_VALUE || src0.nr < XE2_MAX_GRF);
assert(src1.file != BRW_IMMEDIATE_VALUE && src1.nr < XE2_MAX_GRF);
assert(src2.file == BRW_IMMEDIATE_VALUE || src2.nr < XE2_MAX_GRF);
assert(dest.address_mode == BRW_ADDRESS_DIRECT);
assert(src0.address_mode == BRW_ADDRESS_DIRECT);
assert(src1.address_mode == BRW_ADDRESS_DIRECT);

2
src/intel/compiler/brw_fs_scoreboard.cpp
View file

@ -754,7 +754,7 @@ namespace {
}
private:
dependency grf_deps[BRW_MAX_GRF];
dependency grf_deps[XE2_MAX_GRF];
dependency addr_dep;
dependency accum_dep;

2
src/intel/compiler/brw_ir_performance.cpp
View file

@ -72,7 +72,7 @@ namespace {
/* Register part of the GRF. */
EU_DEPENDENCY_ID_GRF0 = 0,
/* Register part of the MRF. Only used on Gfx4-6. */
EU_DEPENDENCY_ID_MRF0 = EU_DEPENDENCY_ID_GRF0 + BRW_MAX_GRF,
EU_DEPENDENCY_ID_MRF0 = EU_DEPENDENCY_ID_GRF0 + XE2_MAX_GRF,
/* Address register part of the ARF. */
EU_DEPENDENCY_ID_ADDR0 = EU_DEPENDENCY_ID_MRF0 + 24,
/* Accumulator register part of the ARF. */

5
src/intel/compiler/brw_reg.h
View file

@ -57,8 +57,9 @@ extern "C" {
struct intel_device_info;
/** Number of general purpose registers (VS, WM, etc) */
/** Size of general purpose register space in REG_SIZE units */
#define BRW_MAX_GRF 128
#define XE2_MAX_GRF 256
/**
* First GRF used for the MRF hack.
@ -417,7 +418,7 @@ brw_reg(enum brw_reg_file file,
{
struct brw_reg reg;
if (file == BRW_GENERAL_REGISTER_FILE)
assert(nr < BRW_MAX_GRF);
assert(nr < XE2_MAX_GRF);
else if (file == BRW_ARCHITECTURE_REGISTER_FILE)
assert(nr <= BRW_ARF_TIMESTAMP);
/* Asserting on the MRF register number requires to know the hardware gen