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ir3: fix spill/reload split src/dst regs

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When splitting spills/reloads into to multiple separate spills/reloads,
the src/dst registers where not adjusted. This caused the separate
instructions too all refer to the same register.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30613>
This commit is contained in:
Job Noorman 2024-08-12 12:01:09 +02:00 • committed by Marge Bot
parent 092b0ecc2e
commit 2260a4bbba
1 changed files with 4 additions and 0 deletions
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4
src/freedreno/ir3/ir3_lower_spill.c
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@ -139,6 +139,8 @@ split_spill(struct ir3_instruction *spill)
if (clone->srcs[1]->flags & IR3_REG_ARRAY) {
clone->srcs[1]->num = clone->srcs[1]->array.base + comp;
clone->srcs[1]->flags &= ~IR3_REG_ARRAY;
} else {
clone->srcs[1]->num += comp;
}
clone->srcs[2]->uim_val = components;
@ -173,6 +175,8 @@ split_reload(struct ir3_instruction *reload)
if (clone->dsts[0]->flags & IR3_REG_ARRAY) {
clone->dsts[0]->num = clone->dsts[0]->array.base + comp;
clone->dsts[0]->flags &= ~IR3_REG_ARRAY;
} else {
clone->dsts[0]->num += comp;
}
clone->srcs[2]->uim_val = components;